PERF-LIST(1) perf Manual PERF-LIST(1) (NAME) perf-list - (SYNOPSIS) perf list [] [hw|sw|cache|tracepoint|pmu|sdt|metric|metricgroup|event_glob] (DESCRIPTION) perf -e . (OPTIONS) -d, --desc . () --no-desc . -v, --long-desc PMU -. --debug . --details perf perf stat. --deprecated . . --unit PMU PMU . ( : --unit cpu --unit msr --unit cpu_core --unit cpu_atom) -j, --json JSON. -o, --output= . stdout . (EVENT MODIFIERS) . . : u - (user-space) k - (kernel) h - (hypervisor) I - (non-idle) G - ( KVM) H - ( KVM) p - (precise level) P - S - (PERF_SAMPLE_READ) D - PMU W - e - PMU b - BPF ( perf stat --bpf-counters) R - (retire latency) X - PMU p . p : 0 - SAMPLE_IP (skid) 1 - SAMPLE_IP 2 - SAMPLE_IP 3 - SAMPLE_IP (sample shadowing) . Intel PEBS . AMD IBS OP ( ) . Intel PEBS PMU AMD IBS . ( ibs_op// ibs_op//p ibs_op//pp ibs_op//ppp ). precise 0x76 (cpu-cycles CPU) 0xC1 (micro-ops retired) . IBS ( IBS op) IBS Op (IbsOpCntCtl) ( Core Complex (CCX) -> Processor x86 Core -> Instruction Based Sampling (IBS) [AMD Processor Programming Reference (PPR)] stepping ). Manual Volume 2: System Programming, 13.3 Instruction-Based Sampling). IBS: perf record -a -e cpu-cycles:p ... # use ibs op counting cycles perf record -a -e r076:p ... # same as -e cpu-cycles:p perf record -a -e r0C1:p ... # use ibs op counting micro-ops perf . x86 N MSR IA32_PERFEVTSELx ( [Intel(R) 64 and IA-32 Architectures Software Developer's Manual Volume 3B: System Programming Guide] 30-1 MSR IA32_PERFEVTSELx) MSR PERF_CTL AMD ( Core Complex (CCX) -> Processor x86 Core -> MSR Registers [AMD Processor Programming Reference (PPR)] stepping ) . : x86 : event umask edge inv cmask. guest/host only OS/user mode EVENT MODIFIERS . : Intel Core i7 QM720 : Event Umask Event Mask Num. Value Mnemonic Description Comment A8H 01H LSD.UOPS Counts the number of micro-ops Use cmask=1 and delivered by loop stream detector invert to count cycles 0x1A8 : perf stat -e r1a8 -a sleep 1 perf record -e r1a8 ... pmu : perf record -e r1a8 -a sleep 1 perf record -e cpu/r1a8/ ... perf record -e cpu/r0x1a8/ ... AMD unit mask . : cat /sys/bus/event_source/devices//format/ : AMD EPYC 7713 : Event Umask Event Mask Num. Value Mnemonic Description 28FH 03H op_cache_hit_miss.op_cache_hit Counts Op Cache micro-tag hit events. 0x0328F (nibble) EventSelect 32-35 : cat /sys/bus/event_source/devices/cpu/format/event 0x20000038F : perf stat -e r20000038f -a sleep 1 perf record -e r20000038f ... pmu : perf record -e r20000038f -a sleep 1 perf record -e cpu/r20000038f/ ... perf record -e cpu/r0x20000038f/ ... . << (SEE ALSO)>> ..SH " PMU (ARBITRARY PMUS)" perf (syntax) PMU . CPU . PMU : ls /sys/bus/event_source/devices/*/format "LSD.UOPS" PMU : perf stat -e cpu/event=0xa8,umask=0x1,name=LSD.UOPS_CYCLES,cmask=0x1/ ... perf stat -e cpu/event=0xa8,umask=0x1,cmask=0x1,name=\'LSD.UOPS_CYCLES:cmask=0x1\'/ ... PMU (PER SOCKET PMUS) PMU CPU . PMU perf stat -a . CPU . 0 Intel Xeon : perf stat -C 0 -a uncore_imc_0/cas_count_read/,uncore_imc_0/cas_count_write/ -I 1000 ... PMU . PMU imc ( perf list ) . (glob) PMU uncore_ . : perf stat -C 0 -a imc/cas_count_read/,imc/cas_count_write/ -I 1000 ... perf stat -C 0 -a *imc*/cas_count_read/,*imc*/cas_count_write/ -I 1000 ... : perf stat -I 1000 -e power/energy-cores/ -a (ACCESS RESTRICTIONS) (non-root) PMU (context-switched) . PMU (cpu) cycles instructions . PMU (root) . "any" . sysctl kernel.perf_event_paranoid -1 . (tracepoint) perf /sys/kernel/tracing perf_event_paranoid . /HWMON (TOOL/HWMON EVENTS) PMU perf_event_open . perf stat . (Tool events) . duration_time user_time system_time num_cpus_online . Hwmon sysfs hwmon /sys/class/hwmon . . (TRACING) PMU Intel PT (low overhead) . intel-pt.txt . (PARAMETERIZED EVENTS) PMU perf-list ? . : hv_gpci/dtbp_ptitc,phys_processor_idx=?/ ? . : perf stat -C 0 -e 'hv_gpci/dtbp_ptitc,phys_processor_idx=0x2/' ... : percore: : perf stat -e cpu/event=0,umask=0x3,percore=1/ cpu: CPU CPU . PMU CPU . CPU . : instructions CPU 0 2 cycles CPU 1 2: perf stat -e instructions/cpu=0,cpu=2/,cycles/cpu=1-2/ -a sleep 1 : uncore data_read CPU 0 uncore data_write CPU 1: perf stat -e data_read/cpu=0/,data_write/cpu=1/ -a sleep 1 : msr/tsc/ CPU PMU cpu_core : perf stat -e msr/tsc,cpu=cpu_core/ -a sleep 1 (EVENT GROUPS) perf (multiplexing) . . . { } . perf stat -e '{instructions,cycles}' ... CPU . . Intel Core instructions cycles ref-cycles. . . (Globally pinned) . x86 NMI watchdog . watchdog (root) : echo 0 > /proc/sys/kernel/nmi_watchdog PMU . (LEADER SAMPLING) perf :S . perf record -e '{cycles,instructions}:S' ... perf report --group :S ( leader) . AUX ( Intel PT CoreSight) AUX . (OPTIONS) . : 1. hw hardware cache-misses . 2. sw software context switches . 3. cache hwcache L1-dcache-loads . 4. tracepoint tracepoint subsys_glob:event_glob tracepoint sched block . 5. pmu PMU . 6. sdt Statically Defined Tracepoint. 7. metric 8. metricgroup . 9. (glob) . 10. . . : 1. --raw-dump (raw-dump) . 2. --raw-dump [hw|sw|cache|tracepoint|pmu|event_glob] (raw-dump) . (INTEL AUTO COUNTER RELOAD SUPPORT) Intel Auto Counter Reload perf (Auto counter reload) . . (sample period) ("acr_mask") . IPC > 2 : perf record -e {cpu_atom/instructions,period=200000,acr_mask=0x2/, \ cpu_atom/cycles,period=100000,acr_mask=0x3/} -- true "instructions" 200000 "cycles" . "cycles" . IPC > 2 . acr_mask . "instructions" acr_mask 0x2 . "cycles" acr_mask 0x3 . RATIO-TO-PREV (RATIO-TO-PREV EVENT TERM) "ratio-to-prev" n -c/--count . . : PMU . : perf record -e {cpu_atom/instructions/, \ cpu_atom/cycles,period=100000,ratio-to-prev=0.5/} -- true ratio-to-prev 1:0.5 2:1 . IPC < 2 : perf record -e {cpu_atom/cycles/, \ cpu_atom/instructions,period=200000,ratio-to-prev=2.0/} -- true (SEE ALSO) perf-stat(1), perf-top(1), perf-record(1), Intel(R) 64 and IA-32 Architectures Software Developer's Manual Volume 3B: System Programming Guide[1], AMD Processor Programming Reference (PPR)[2].SH " (NOTES)" 1. Intel(R) 64 IA-32 3B: http://www.intel.com/sdm 2. AMD (PPR) https://bugzilla.kernel.org/show_bug.cgi?id=206537 perf 09/04/2026 PERF-LIST(1)