PERF-C2C(1) perf Manual PERF-C2C(1) (NAME) perf-c2c - C2C/HITM (SYNOPSIS) perf c2c record [] perf c2c record [] -- [] perf c2c report [] (DESCRIPTION) C2C Cache To Cache ( ) . perf c2c C2C/HITM . (cacheline contentions) . Intel (load latency) (precise store facility) Intel . PowerPC . AMD IBS op pmu ( perf c2c Zen3 ). Arm64 SPE (load) (store) . perf-arm-spe(1) . Arm SPE . : - - ( load store) - ( ) c2c - HITM - . record/report . record report . (RECORD OPTIONS) -e, --event= PMU. perf c2c record -e list . -v, --verbose ( ). -l, --ldlat mem-loads. Intel Arm64 AMD . . AMD: - /sys/bus/event_source/devices/ibs_op/caps/ldlat '1' . - 128 2048 ( ) . - 128 profiling . - (load latency) . -k, --all-kernel (kernel space). -u, --all-user (user space). -k, --vmlinux= vmlinux -v, --verbose ( ). -i, --input . -N, --node-info ( NODE INFO ) -c, --coalesce (cacheline). : tid pid iaddr dso ( COALESCE ) -g, --call-graph (callchains). perf-report . --stdio stdio ( STDIO OUTPUT ) --stats stdio. --full-symbols . --no-source Source:Line. --show-all HITM 0.0005 HITM. -f, --force . -d, --display HITM (rmt lcl) (peer) . HITM (tot) Arm64 peer . --stitch-lbr LBR (stitched) . perf.data perf c2c record --call-graph lbr . . lbr . . . setjmp/longjmp / . --double-cl (cacheline) . Adjacent Cacheline Prefetch . -M, --disassembler-style= objdump. --objdump= objdump. perf c2c record cacheline HITM perf record . perf record : ( perf record ) -W,-d,--phys-data,--sample-cpu . -e . +--------+---------------+-----------------+--------------------------------------------------------------------------------+ | Arch | Configuration | Options | Events | +--------+---------------+-----------------+--------------------------------------------------------------------------------+ | Intel | Default | -e ldlat-loads | cpu/mem-loads,ldlat=30/P | | | | -e ldlat-stores | cpu/mem-stores/P | | |---------------+-----------------+------------------------------------------------------------------------------+ | | Load only | -e ldlat-loads | cpu/mem-loads,ldlat=30/P | | |---------------+-----------------+------------------------------------------------------------------------------+ | | Store only | -e ldlat-stores | cpu/mem-stores/P | +--------+---------------+-----------------+--------------------------------------------------------------------------------+ | Intel | Default | -e ldlat-loads | {cpu/mem-loads-aux/,cpu/mem-loads,ldlat=30/}:P | | with | | -e ldlat-stores | cpu/mem-stores/P | | AUX |--------------+------------------+------------------------------------------------------------------------------+ | | Load only | -e ldlat-loads | {cpu/mem-loads-aux/,cpu/mem-loads,ldlat=30/}:P | | |---------------+-----------------+------------------------------------------------------------------------------+ | | Store only | -e ldlat-stores | cpu/mem-stores/P | +--------+---------------+-----------------+--------------------------------------------------------------------------------+ | AMD | Default | -e mem-ldst | ibs_op// (without latency support) | | | | | ibs_op/ldlat=30/ (with latency support) | +--------+---------------+-----------------+--------------------------------------------------------------------------------+ | PowerPC| Default | -e ldlat-loads | cpu/mem-loads/ | | | | -e ldlat-stores | cpu/mem-stores/ | | |---------------+-----------------+------------------------------------------------------------------------------+ | | Load only | -e ldlat-loads | cpu/mem-loads/ | | |---------------+-----------------+------------------------------------------------------------------------------+ | | Store only | -e ldlat-stores | cpu/mem-stores/ | +--------+---------------+-----------------+--------------------------------------------------------------------------------+ | Arm | Default | -e spe-ldst | arm_spe_0/ts_enable=1,pa_enable=1,load_filter=1,store_filter=1,min_latency=30/ | | SPE |---------------+-----------------+------------------------------------------------------------------------------+ | | Load only | -e spe-load | arm_spe_0/ts_enable=1,pa_enable=1,load_filter=1,min_latency=30/ | | |---------------+-----------------+------------------------------------------------------------------------------+ | | Store only | -e spe-store | arm_spe_0/ts_enable=1,pa_enable=1,store_filter=1/ | +--------+---------------+-----------------+--------------------------------------------------------------------------------+ perf record -- ( ): $ perf c2c record -- -g -a c2c record RECORD OPTIONS . C2C REPORT perf c2c report . : stdio tui (). report : - cacheline - cacheline - cacheline - perf report : ) cacheline ) cacheline cacheline ) : ( stdio TUI ) Index - cacheline Cacheline - cacheline ( ) Rmt/Lcl Hitm ( HITM) - cacheline / HITM Peer Snoop ( peer) - cacheline (peer) LLC Load Hitm - Total, LclHitm, RmtHitm ( HITM) - HITM // Load Peer - Total, Local, Remote ( peer) - // DRAM Total records - cacheline Total loads - (load) Total stores - (store) Store Reference - L1Hit, L1Miss, N/A L1Hit - store L1 L1Miss - store L1 N/A - store Core Load Hit - FB, L1, L2 - (load hits) L1 FB ( ) L2 LLC Load Hit - LlcHit, LclHitm - LLC LLC HITM LLC RMT Load Hit - RmtHit, RmtHitm - (remote) HITM Arm neoverse RmtHit DRAM Load Dram - Lcl, Rmt - (local) (remote) DRAM ) : HITM - Rmt, Lcl ( HITM) - HITM / (cacheline) Peer Snoop - Rmt, Lcl ( peer) - (peer) / (cacheline) Store Refs - L1 Hit, L1 Miss, N/A - store L1 L1 (N/A) Data address - Offset - (offset address) Pid - (pid) Tid - (tid) Code address - cycles - rmt hitm, lcl hitm, load ( HITM) - - HITM / cycles - rmt peer, lcl peer, load ( peer) - - / cpu cnt - Symbol - 'Code address' Shared Object - 'Code address' Source:Line - 'Code address' Node - ( (NODE INFO) ) (NODE INFO) Node (cacheline) . : - , - : Node{cpus %hitms %stores} ( HITM) Node{cpus %peers %stores} ( peer) - : Node{cpu list} -N n TUI . (COALESCE) . : tid - TID pid - PID iaddr - : Code address, Code symbol, Shared Object, Source line dso - (shared object) pid,iaddr . STDIO (STDIO OUTPUT) stdio . : Trace Event Information - Global Shared Cache Line Event Information - Shared Data Cache Line Table - Shared Cache Line Distribution Pareto - TUI (cachelines) (offset) . ? . (CREDITS) Don Zickus Dick Fowles Joe Mario Arnaldo Carvalho de Melo Stephane Eranian Jiri Olsa Andi Kleen . C2C (C2C BLOG) Joe c2c : https://joemario.github.io/blog/2016/09/01/c2c-blog (SEE ALSO) perf-record(1), perf-mem(1), perf-arm-spe(1) perf 09/04/2026 PERF-C2C(1)