.TH "libcpuid" 3 "libcpuid" \" -*- nroff -*- .ad l .nh .SH NAME libcpuid \- LibCPUID .PP \- LibCPUID provides CPU identification\&. .SH SYNOPSIS .br .PP .SS "Data Structures" .in +1c .ti -1c .RI "struct \fBcpu_raw_data_t\fP" .br .RI "Contains just the raw CPUID data\&. " .ti -1c .RI "struct \fBcpu_raw_data_array_t\fP" .br .RI "Contains an array of raw CPUID data\&. " .ti -1c .RI "struct \fBcpu_sgx_t\fP" .br .RI "This contains information about SGX features of the processor Example usage: " .ti -1c .RI "struct \fBx86_id_t\fP" .br .RI "Contains x86 specific info\&. " .ti -1c .RI "struct \fBarm_id_t\fP" .br .RI "Contains ARM specific info\&. " .ti -1c .RI "struct \fBcpu_id_t\fP" .br .RI "This contains the recognized CPU features/info\&. " .ti -1c .RI "struct \fBsystem_id_t\fP" .br .RI "This contains the recognized features/info for all CPUs on the system\&. " .ti -1c .RI "struct \fBcpu_mark_t\fP" .br .RI "Internal structure, used in cpu_tsc_mark, cpu_tsc_unmark and cpu_clock_by_mark\&. " .ti -1c .RI "struct \fBcpu_epc_t\fP" .br .RI "The return value of \fBcpuid_get_epc()\fP\&. " .ti -1c .RI "struct \fBcpu_list_t\fP" .br .RI "a structure that holds a list of processor names " .in -1c .SS "Macros" .in +1c .ti -1c .RI "#define \fBLIBCPUID_DEPRECATED\fP(message)" .br .ti -1c .RI "#define \fBNUM_CPU_VENDORS\fP NUM_CPU_VENDORS" .br .ti -1c .RI "#define \fBNUM_CPU_ARCHITECTURES\fP NUM_CPU_ARCHITECTURES" .br .ti -1c .RI "#define \fBNUM_FEATURE_LEVELS\fP NUM_FEATURE_LEVELS" .br .ti -1c .RI "#define \fBNUM_CPU_PURPOSES\fP NUM_CPU_PURPOSES" .br .ti -1c .RI "#define \fBNUM_HYPERVISOR_VENDORS\fP NUM_HYPERVISOR_VENDORS" .br .ti -1c .RI "#define \fBCPU_INVALID_VALUE\fP 0x3fffffff" .br .in -1c .SS "Typedefs" .in +1c .ti -1c .RI "typedef void(* \fBlibcpuid_warn_fn_t\fP) (const char *msg)" .br .in -1c .SS "Enumerations" .in +1c .ti -1c .RI "enum \fBcpu_vendor_t\fP { \fBVENDOR_INTEL\fP = 0, \fBVENDOR_AMD\fP, \fBVENDOR_CYRIX\fP, \fBVENDOR_NEXGEN\fP, \fBVENDOR_TRANSMETA\fP, \fBVENDOR_UMC\fP, \fBVENDOR_CENTAUR\fP, \fBVENDOR_RISE\fP, \fBVENDOR_SIS\fP, \fBVENDOR_NSC\fP, \fBVENDOR_HYGON\fP, \fBVENDOR_ARM\fP, \fBVENDOR_BROADCOM\fP, \fBVENDOR_CAVIUM\fP, \fBVENDOR_DEC\fP, \fBVENDOR_FUJITSU\fP, \fBVENDOR_HISILICON\fP, \fBVENDOR_INFINEON\fP, \fBVENDOR_FREESCALE\fP, \fBVENDOR_NVIDIA\fP, \fBVENDOR_APM\fP, \fBVENDOR_QUALCOMM\fP, \fBVENDOR_SAMSUNG\fP, \fBVENDOR_MARVELL\fP, \fBVENDOR_APPLE\fP, \fBVENDOR_FARADAY\fP, \fBVENDOR_MICROSOFT\fP, \fBVENDOR_PHYTIUM\fP, \fBVENDOR_AMPERE\fP, \fBNUM_CPU_VENDORS\fP, \fBVENDOR_UNKNOWN\fP = -1 }" .br .RI "CPU vendor, as guessed from the Vendor String\&. " .ti -1c .RI "enum \fBcpu_architecture_t\fP { \fBARCHITECTURE_X86\fP = 0, \fBARCHITECTURE_ARM\fP, \fBNUM_CPU_ARCHITECTURES\fP, \fBARCHITECTURE_UNKNOWN\fP = -1 }" .br .RI "CPU architecture\&. " .ti -1c .RI "enum \fBcpu_feature_level_t\fP { \fBFEATURE_LEVEL_I386\fP, \fBFEATURE_LEVEL_I486\fP, \fBFEATURE_LEVEL_I586\fP, \fBFEATURE_LEVEL_I686\fP, \fBFEATURE_LEVEL_X86_64_V1\fP, \fBFEATURE_LEVEL_X86_64_V2\fP, \fBFEATURE_LEVEL_X86_64_V3\fP, \fBFEATURE_LEVEL_X86_64_V4\fP, \fBFEATURE_LEVEL_ARM_V1\fP = 100, \fBFEATURE_LEVEL_ARM_V2\fP, \fBFEATURE_LEVEL_ARM_V3\fP, \fBFEATURE_LEVEL_ARM_V4\fP, \fBFEATURE_LEVEL_ARM_V4T\fP, \fBFEATURE_LEVEL_ARM_V5\fP, \fBFEATURE_LEVEL_ARM_V5T\fP, \fBFEATURE_LEVEL_ARM_V5TE\fP, \fBFEATURE_LEVEL_ARM_V5TEJ\fP, \fBFEATURE_LEVEL_ARM_V6\fP, \fBFEATURE_LEVEL_ARM_V6_M\fP, \fBFEATURE_LEVEL_ARM_V7_A\fP, \fBFEATURE_LEVEL_ARM_V7_M\fP, \fBFEATURE_LEVEL_ARM_V7_R\fP, \fBFEATURE_LEVEL_ARM_V7E_M\fP, \fBFEATURE_LEVEL_ARM_V8_0_A\fP, \fBFEATURE_LEVEL_ARM_V8_0_M\fP, \fBFEATURE_LEVEL_ARM_V8_0_R\fP, \fBFEATURE_LEVEL_ARM_V8_1_A\fP, \fBFEATURE_LEVEL_ARM_V8_1_M\fP, \fBFEATURE_LEVEL_ARM_V8_2_A\fP, \fBFEATURE_LEVEL_ARM_V8_3_A\fP, \fBFEATURE_LEVEL_ARM_V8_4_A\fP, \fBFEATURE_LEVEL_ARM_V8_5_A\fP, \fBFEATURE_LEVEL_ARM_V8_6_A\fP, \fBFEATURE_LEVEL_ARM_V8_7_A\fP, \fBFEATURE_LEVEL_ARM_V8_8_A\fP, \fBFEATURE_LEVEL_ARM_V8_9_A\fP, \fBFEATURE_LEVEL_ARM_V9_0_A\fP, \fBFEATURE_LEVEL_ARM_V9_1_A\fP, \fBFEATURE_LEVEL_ARM_V9_2_A\fP, \fBFEATURE_LEVEL_ARM_V9_3_A\fP, \fBFEATURE_LEVEL_ARM_V9_4_A\fP, \fBFEATURE_LEVEL_ARM_V9_5_A\fP, \fBNUM_FEATURE_LEVELS\fP, \fBFEATURE_LEVEL_UNKNOWN\fP = -1 }" .br .RI "CPU feature level\&. " .ti -1c .RI "enum \fBcpu_purpose_t\fP { \fBPURPOSE_GENERAL\fP = 0, \fBPURPOSE_PERFORMANCE\fP, \fBPURPOSE_EFFICIENCY\fP, \fBPURPOSE_LP_EFFICIENCY\fP, \fBPURPOSE_U_PERFORMANCE\fP, \fBNUM_CPU_PURPOSES\fP }" .br .RI "CPU purpose\&. " .ti -1c .RI "enum \fBhypervisor_vendor_t\fP { \fBHYPERVISOR_NONE\fP = 0, \fBHYPERVISOR_BHYVE\fP, \fBHYPERVISOR_HYPERV\fP, \fBHYPERVISOR_KVM\fP, \fBHYPERVISOR_PARALLELS\fP, \fBHYPERVISOR_QEMU\fP, \fBHYPERVISOR_VIRTUALBOX\fP, \fBHYPERVISOR_VMWARE\fP, \fBHYPERVISOR_XEN\fP, \fBNUM_HYPERVISOR_VENDORS\fP, \fBHYPERVISOR_UNKNOWN\fP = -1 }" .br .RI "Hypervisor vendor, as guessed from the CPU_FEATURE_HYPERVISOR flag\&. " .ti -1c .RI "enum \fBcpu_feature_t\fP { \fBCPU_FEATURE_FPU\fP = 0, \fBCPU_FEATURE_VME\fP, \fBCPU_FEATURE_DE\fP, \fBCPU_FEATURE_PSE\fP, \fBCPU_FEATURE_TSC\fP, \fBCPU_FEATURE_MSR\fP, \fBCPU_FEATURE_PAE\fP, \fBCPU_FEATURE_MCE\fP, \fBCPU_FEATURE_CX8\fP, \fBCPU_FEATURE_APIC\fP, \fBCPU_FEATURE_MTRR\fP, \fBCPU_FEATURE_SEP\fP, \fBCPU_FEATURE_PGE\fP, \fBCPU_FEATURE_MCA\fP, \fBCPU_FEATURE_CMOV\fP, \fBCPU_FEATURE_PAT\fP, \fBCPU_FEATURE_PSE36\fP, \fBCPU_FEATURE_PN\fP, \fBCPU_FEATURE_CLFLUSH\fP, \fBCPU_FEATURE_DTS\fP, \fBCPU_FEATURE_ACPI\fP, \fBCPU_FEATURE_MMX\fP, \fBCPU_FEATURE_FXSR\fP, \fBCPU_FEATURE_SSE\fP, \fBCPU_FEATURE_SSE2\fP, \fBCPU_FEATURE_SS\fP, \fBCPU_FEATURE_HT\fP, \fBCPU_FEATURE_TM\fP, \fBCPU_FEATURE_IA64\fP, \fBCPU_FEATURE_PBE\fP, \fBCPU_FEATURE_PNI\fP, \fBCPU_FEATURE_PCLMUL\fP, \fBCPU_FEATURE_DTS64\fP, \fBCPU_FEATURE_MONITOR\fP, \fBCPU_FEATURE_DS_CPL\fP, \fBCPU_FEATURE_VMX\fP, \fBCPU_FEATURE_SMX\fP, \fBCPU_FEATURE_EST\fP, \fBCPU_FEATURE_TM2\fP, \fBCPU_FEATURE_SSSE3\fP, \fBCPU_FEATURE_CID\fP, \fBCPU_FEATURE_CX16\fP, \fBCPU_FEATURE_XTPR\fP, \fBCPU_FEATURE_PDCM\fP, \fBCPU_FEATURE_DCA\fP, \fBCPU_FEATURE_SSE4_1\fP, \fBCPU_FEATURE_SSE4_2\fP, \fBCPU_FEATURE_SYSCALL\fP, \fBCPU_FEATURE_XD\fP, \fBCPU_FEATURE_MOVBE\fP, \fBCPU_FEATURE_POPCNT\fP, \fBCPU_FEATURE_AES\fP, \fBCPU_FEATURE_XSAVE\fP, \fBCPU_FEATURE_OSXSAVE\fP, \fBCPU_FEATURE_AVX\fP, \fBCPU_FEATURE_MMXEXT\fP, \fBCPU_FEATURE_3DNOW\fP, \fBCPU_FEATURE_3DNOWEXT\fP, \fBCPU_FEATURE_NX\fP, \fBCPU_FEATURE_FXSR_OPT\fP, \fBCPU_FEATURE_RDTSCP\fP, \fBCPU_FEATURE_LM\fP, \fBCPU_FEATURE_LAHF_LM\fP, \fBCPU_FEATURE_CMP_LEGACY\fP, \fBCPU_FEATURE_SVM\fP, \fBCPU_FEATURE_ABM\fP, \fBCPU_FEATURE_MISALIGNSSE\fP, \fBCPU_FEATURE_SSE4A\fP, \fBCPU_FEATURE_3DNOWPREFETCH\fP, \fBCPU_FEATURE_OSVW\fP, \fBCPU_FEATURE_IBS\fP, \fBCPU_FEATURE_SSE5\fP, \fBCPU_FEATURE_SKINIT\fP, \fBCPU_FEATURE_WDT\fP, \fBCPU_FEATURE_TS\fP, \fBCPU_FEATURE_FID\fP, \fBCPU_FEATURE_VID\fP, \fBCPU_FEATURE_TTP\fP, \fBCPU_FEATURE_TM_AMD\fP, \fBCPU_FEATURE_STC\fP, \fBCPU_FEATURE_100MHZSTEPS\fP, \fBCPU_FEATURE_HWPSTATE\fP, \fBCPU_FEATURE_CONSTANT_TSC\fP, \fBCPU_FEATURE_XOP\fP, \fBCPU_FEATURE_FMA3\fP, \fBCPU_FEATURE_FMA4\fP, \fBCPU_FEATURE_TBM\fP, \fBCPU_FEATURE_F16C\fP, \fBCPU_FEATURE_RDRAND\fP, \fBCPU_FEATURE_X2APIC\fP, \fBCPU_FEATURE_CPB\fP, \fBCPU_FEATURE_APERFMPERF\fP, \fBCPU_FEATURE_PFI\fP, \fBCPU_FEATURE_PA\fP, \fBCPU_FEATURE_AVX2\fP, \fBCPU_FEATURE_BMI1\fP, \fBCPU_FEATURE_BMI2\fP, \fBCPU_FEATURE_HLE\fP, \fBCPU_FEATURE_RTM\fP, \fBCPU_FEATURE_AVX512F\fP, \fBCPU_FEATURE_AVX512DQ\fP, \fBCPU_FEATURE_AVX512PF\fP, \fBCPU_FEATURE_AVX512ER\fP, \fBCPU_FEATURE_AVX512CD\fP, \fBCPU_FEATURE_SHA_NI\fP, \fBCPU_FEATURE_AVX512BW\fP, \fBCPU_FEATURE_AVX512VL\fP, \fBCPU_FEATURE_SGX\fP, \fBCPU_FEATURE_RDSEED\fP, \fBCPU_FEATURE_ADX\fP, \fBCPU_FEATURE_AVX512VNNI\fP, \fBCPU_FEATURE_AVX512VBMI\fP, \fBCPU_FEATURE_AVX512VBMI2\fP, \fBCPU_FEATURE_HYPERVISOR\fP, \fBCPU_FEATURE_SWAP\fP, \fBCPU_FEATURE_THUMB\fP, \fBCPU_FEATURE_ADVMULTU\fP, \fBCPU_FEATURE_ADVMULTS\fP, \fBCPU_FEATURE_JAZELLE\fP, \fBCPU_FEATURE_DEBUGV6\fP, \fBCPU_FEATURE_DEBUGV6P1\fP, \fBCPU_FEATURE_THUMB2\fP, \fBCPU_FEATURE_DEBUGV7\fP, \fBCPU_FEATURE_DEBUGV7P1\fP, \fBCPU_FEATURE_THUMBEE\fP, \fBCPU_FEATURE_DIVIDE\fP, \fBCPU_FEATURE_LPAE\fP, \fBCPU_FEATURE_PMUV1\fP, \fBCPU_FEATURE_PMUV2\fP, \fBCPU_FEATURE_ASID16\fP, \fBCPU_FEATURE_ADVSIMD\fP, \fBCPU_FEATURE_CRC32\fP, \fBCPU_FEATURE_CSV2_1P1\fP, \fBCPU_FEATURE_CSV2_1P2\fP, \fBCPU_FEATURE_CSV2_2\fP, \fBCPU_FEATURE_CSV2_3\fP, \fBCPU_FEATURE_DOUBLELOCK\fP, \fBCPU_FEATURE_ETS2\fP, \fBCPU_FEATURE_FP\fP, \fBCPU_FEATURE_MIXEDEND\fP, \fBCPU_FEATURE_MIXEDENDEL0\fP, \fBCPU_FEATURE_PMULL\fP, \fBCPU_FEATURE_PMUV3\fP, \fBCPU_FEATURE_SHA1\fP, \fBCPU_FEATURE_SHA256\fP, \fBCPU_FEATURE_NTLBPA\fP, \fBCPU_FEATURE_HAFDBS\fP, \fBCPU_FEATURE_HPDS\fP, \fBCPU_FEATURE_LOR\fP, \fBCPU_FEATURE_LSE\fP, \fBCPU_FEATURE_PAN\fP, \fBCPU_FEATURE_PMUV3P1\fP, \fBCPU_FEATURE_RDM\fP, \fBCPU_FEATURE_VHE\fP, \fBCPU_FEATURE_VMID16\fP, \fBCPU_FEATURE_AA32HPD\fP, \fBCPU_FEATURE_AA32I8MM\fP, \fBCPU_FEATURE_DPB\fP, \fBCPU_FEATURE_DEBUGV8P2\fP, \fBCPU_FEATURE_F32MM\fP, \fBCPU_FEATURE_F64MM\fP, \fBCPU_FEATURE_FP16\fP, \fBCPU_FEATURE_HPDS2\fP, \fBCPU_FEATURE_I8MM\fP, \fBCPU_FEATURE_IESB\fP, \fBCPU_FEATURE_LPA\fP, \fBCPU_FEATURE_LSMAOC\fP, \fBCPU_FEATURE_LVA\fP, \fBCPU_FEATURE_PAN2\fP, \fBCPU_FEATURE_RAS\fP, \fBCPU_FEATURE_SHA3\fP, \fBCPU_FEATURE_SHA512\fP, \fBCPU_FEATURE_SM3\fP, \fBCPU_FEATURE_SM4\fP, \fBCPU_FEATURE_SPE\fP, \fBCPU_FEATURE_SVE\fP, \fBCPU_FEATURE_TTCNP\fP, \fBCPU_FEATURE_UAO\fP, \fBCPU_FEATURE_XNX\fP, \fBCPU_FEATURE_CCIDX\fP, \fBCPU_FEATURE_CONSTPACFIELD\fP, \fBCPU_FEATURE_EPAC\fP, \fBCPU_FEATURE_FCMA\fP, \fBCPU_FEATURE_FPAC\fP, \fBCPU_FEATURE_FPACCOMBINE\fP, \fBCPU_FEATURE_JSCVT\fP, \fBCPU_FEATURE_LRCPC\fP, \fBCPU_FEATURE_PACIMP\fP, \fBCPU_FEATURE_PACQARMA3\fP, \fBCPU_FEATURE_PACQARMA5\fP, \fBCPU_FEATURE_PAUTH\fP, \fBCPU_FEATURE_SPEV1P1\fP, \fBCPU_FEATURE_AMUV1\fP, \fBCPU_FEATURE_BBM\fP, \fBCPU_FEATURE_DIT\fP, \fBCPU_FEATURE_DEBUGV8P4\fP, \fBCPU_FEATURE_DOTPROD\fP, \fBCPU_FEATURE_DOUBLEFAULT\fP, \fBCPU_FEATURE_FHM\fP, \fBCPU_FEATURE_FLAGM\fP, \fBCPU_FEATURE_IDST\fP, \fBCPU_FEATURE_LRCPC2\fP, \fBCPU_FEATURE_LSE2\fP, \fBCPU_FEATURE_MPAM\fP, \fBCPU_FEATURE_PMUV3P4\fP, \fBCPU_FEATURE_RASV1P1\fP, \fBCPU_FEATURE_S2FWB\fP, \fBCPU_FEATURE_SEL2\fP, \fBCPU_FEATURE_TLBIOS\fP, \fBCPU_FEATURE_TLBIRANGE\fP, \fBCPU_FEATURE_TRF\fP, \fBCPU_FEATURE_TTL\fP, \fBCPU_FEATURE_TTST\fP, \fBCPU_FEATURE_BTI\fP, \fBCPU_FEATURE_CSV2\fP, \fBCPU_FEATURE_CSV3\fP, \fBCPU_FEATURE_DPB2\fP, \fBCPU_FEATURE_E0PD\fP, \fBCPU_FEATURE_EVT\fP, \fBCPU_FEATURE_EXS\fP, \fBCPU_FEATURE_FRINTTS\fP, \fBCPU_FEATURE_FLAGM2\fP, \fBCPU_FEATURE_MTE\fP, \fBCPU_FEATURE_MTE2\fP, \fBCPU_FEATURE_PMUV3P5\fP, \fBCPU_FEATURE_RNG\fP, \fBCPU_FEATURE_RNG_TRAP\fP, \fBCPU_FEATURE_SB\fP, \fBCPU_FEATURE_SPECRES\fP, \fBCPU_FEATURE_SSBS\fP, \fBCPU_FEATURE_SSBS2\fP, \fBCPU_FEATURE_AA32BF16\fP, \fBCPU_FEATURE_AMUV1P1\fP, \fBCPU_FEATURE_BF16\fP, \fBCPU_FEATURE_DGH\fP, \fBCPU_FEATURE_ECV\fP, \fBCPU_FEATURE_FGT\fP, \fBCPU_FEATURE_HPMN0\fP, \fBCPU_FEATURE_MPAMV0P1\fP, \fBCPU_FEATURE_MPAMV1P1\fP, \fBCPU_FEATURE_MTPMU\fP, \fBCPU_FEATURE_PAUTH2\fP, \fBCPU_FEATURE_TWED\fP, \fBCPU_FEATURE_AFP\fP, \fBCPU_FEATURE_EBF16\fP, \fBCPU_FEATURE_HCX\fP, \fBCPU_FEATURE_LPA2\fP, \fBCPU_FEATURE_LS64\fP, \fBCPU_FEATURE_LS64_ACCDATA\fP, \fBCPU_FEATURE_LS64_V\fP, \fBCPU_FEATURE_MTE3\fP, \fBCPU_FEATURE_MTE_ASYM_FAULT\fP, \fBCPU_FEATURE_PAN3\fP, \fBCPU_FEATURE_PMUV3P7\fP, \fBCPU_FEATURE_RPRES\fP, \fBCPU_FEATURE_SPEV1P2\fP, \fBCPU_FEATURE_WFXT\fP, \fBCPU_FEATURE_XS\fP, \fBCPU_FEATURE_CMOW\fP, \fBCPU_FEATURE_DEBUGV8P8\fP, \fBCPU_FEATURE_HBC\fP, \fBCPU_FEATURE_MOPS\fP, \fBCPU_FEATURE_NMI\fP, \fBCPU_FEATURE_PMUV3P8\fP, \fBCPU_FEATURE_SCTLR2\fP, \fBCPU_FEATURE_SPEV1P3\fP, \fBCPU_FEATURE_TCR2\fP, \fBCPU_FEATURE_TIDCP1\fP, \fBCPU_FEATURE_ADERR\fP, \fBCPU_FEATURE_AIE\fP, \fBCPU_FEATURE_ANERR\fP, \fBCPU_FEATURE_ATS1A\fP, \fBCPU_FEATURE_CLRBHB\fP, \fBCPU_FEATURE_CSSC\fP, \fBCPU_FEATURE_DEBUGV8P9\fP, \fBCPU_FEATURE_DOUBLEFAULT2\fP, \fBCPU_FEATURE_ECBHB\fP, \fBCPU_FEATURE_FGT2\fP, \fBCPU_FEATURE_HAFT\fP, \fBCPU_FEATURE_LRCPC3\fP, \fBCPU_FEATURE_MTE4\fP, \fBCPU_FEATURE_MTE_ASYNC\fP, \fBCPU_FEATURE_MTE_CANONICAL_TAGS\fP, \fBCPU_FEATURE_MTE_NO_ADDRESS_TAGS\fP, \fBCPU_FEATURE_MTE_PERM\fP, \fBCPU_FEATURE_MTE_STORE_ONLY\fP, \fBCPU_FEATURE_MTE_TAGGED_FAR\fP, \fBCPU_FEATURE_PFAR\fP, \fBCPU_FEATURE_PMUV3_ICNTR\fP, \fBCPU_FEATURE_PMUV3_SS\fP, \fBCPU_FEATURE_PMUV3P9\fP, \fBCPU_FEATURE_PRFMSLC\fP, \fBCPU_FEATURE_RASV2\fP, \fBCPU_FEATURE_RPRFM\fP, \fBCPU_FEATURE_S1PIE\fP, \fBCPU_FEATURE_S1POE\fP, \fBCPU_FEATURE_S2PIE\fP, \fBCPU_FEATURE_S2POE\fP, \fBCPU_FEATURE_SPECRES2\fP, \fBCPU_FEATURE_SPE_DPFZS\fP, \fBCPU_FEATURE_SPEV1P4\fP, \fBCPU_FEATURE_SPMU\fP, \fBCPU_FEATURE_THE\fP, \fBCPU_FEATURE_SVE2\fP, \fBCPU_FEATURE_SVE_AES\fP, \fBCPU_FEATURE_SVE_BITPERM\fP, \fBCPU_FEATURE_SVE_PMULL128\fP, \fBCPU_FEATURE_SVE_SHA3\fP, \fBCPU_FEATURE_SVE_SM4\fP, \fBCPU_FEATURE_TME\fP, \fBCPU_FEATURE_TRBE\fP, \fBCPU_FEATURE_BRBE\fP, \fBCPU_FEATURE_RME\fP, \fBCPU_FEATURE_SME\fP, \fBCPU_FEATURE_SME_F64F64\fP, \fBCPU_FEATURE_SME_FA64\fP, \fBCPU_FEATURE_SME_I16I64\fP, \fBCPU_FEATURE_BRBEV1P1\fP, \fBCPU_FEATURE_MEC\fP, \fBCPU_FEATURE_SME2\fP, \fBCPU_FEATURE_ABLE\fP, \fBCPU_FEATURE_BWE\fP, \fBCPU_FEATURE_D128\fP, \fBCPU_FEATURE_EBEP\fP, \fBCPU_FEATURE_GCS\fP, \fBCPU_FEATURE_ITE\fP, \fBCPU_FEATURE_LSE128\fP, \fBCPU_FEATURE_LVA3\fP, \fBCPU_FEATURE_SEBEP\fP, \fBCPU_FEATURE_SME2P1\fP, \fBCPU_FEATURE_SME_F16F16\fP, \fBCPU_FEATURE_SVE2P1\fP, \fBCPU_FEATURE_SVE_B16B16\fP, \fBCPU_FEATURE_SYSINSTR128\fP, \fBCPU_FEATURE_SYSREG128\fP, \fBCPU_FEATURE_TRBE_EXT\fP, \fBCPU_FEATURE_ASID2\fP, \fBCPU_FEATURE_BWE2\fP, \fBCPU_FEATURE_CPA\fP, \fBCPU_FEATURE_CPA2\fP, \fBCPU_FEATURE_E2H0\fP, \fBCPU_FEATURE_E3DSE\fP, \fBCPU_FEATURE_ETS3\fP, \fBCPU_FEATURE_FAMINMAX\fP, \fBCPU_FEATURE_FGWTE3\fP, \fBCPU_FEATURE_FP8\fP, \fBCPU_FEATURE_FP8DOT2\fP, \fBCPU_FEATURE_FP8DOT4\fP, \fBCPU_FEATURE_FP8FMA\fP, \fBCPU_FEATURE_FPMR\fP, \fBCPU_FEATURE_HACDBS\fP, \fBCPU_FEATURE_HDBSS\fP, \fBCPU_FEATURE_LUT\fP, \fBCPU_FEATURE_PAUTH_LR\fP, \fBCPU_FEATURE_RME_GPC2\fP, \fBCPU_FEATURE_SME_F8F16\fP, \fBCPU_FEATURE_SME_F8F32\fP, \fBCPU_FEATURE_SME_LUTV2\fP, \fBCPU_FEATURE_SPMU2\fP, \fBCPU_FEATURE_SSVE_FP8DOT2\fP, \fBCPU_FEATURE_SSVE_FP8DOT4\fP, \fBCPU_FEATURE_SSVE_FP8FMA\fP, \fBCPU_FEATURE_STEP2\fP, \fBCPU_FEATURE_TLBIW\fP, \fBNUM_CPU_FEATURES\fP }" .br .RI "CPU feature identifiers\&. " .ti -1c .RI "enum \fBcpu_hint_t\fP { \fBCPU_HINT_SSE_SIZE_AUTH\fP = 0, \fBNUM_CPU_HINTS\fP }" .br .RI "CPU detection hints identifiers\&. " .ti -1c .RI "enum \fBcpu_sgx_feature_t\fP { \fBINTEL_SGX1\fP, \fBINTEL_SGX2\fP, \fBNUM_SGX_FEATURES\fP }" .br .RI "SGX features flags\&. " .ti -1c .RI "enum \fBcpu_error_t\fP { \fBERR_OK\fP = 0, \fBERR_NO_CPUID\fP = -1, \fBERR_NO_RDTSC\fP = -2, \fBERR_NO_MEM\fP = -3, \fBERR_OPEN\fP = -4, \fBERR_BADFMT\fP = -5, \fBERR_NOT_IMP\fP = -6, \fBERR_CPU_UNKN\fP = -7, \fBERR_NO_RDMSR\fP = -8, \fBERR_NO_DRIVER\fP = -9, \fBERR_NO_PERMS\fP = -10, \fBERR_EXTRACT\fP = -11, \fBERR_HANDLE\fP = -12, \fBERR_INVMSR\fP = -13, \fBERR_INVCNB\fP = -14, \fBERR_HANDLE_R\fP = -15, \fBERR_INVRANGE\fP = -16, \fBERR_NOT_FOUND\fP = -17, \fBERR_IOCTL\fP = -18, \fBERR_REQUEST\fP = -19 }" .br .RI "Describes common library error codes\&. " .ti -1c .RI "enum \fBcpu_msrinfo_request_t\fP { \fBINFO_MPERF\fP, \fBINFO_APERF\fP, \fBINFO_MIN_MULTIPLIER\fP, \fBINFO_CUR_MULTIPLIER\fP, \fBINFO_MAX_MULTIPLIER\fP, \fBINFO_TEMPERATURE\fP, \fBINFO_THROTTLING\fP, \fBINFO_VOLTAGE\fP, \fBINFO_BCLK\fP, \fBINFO_BUS_CLOCK\fP }" .br .in -1c .SS "Functions" .in +1c .ti -1c .RI "int \fBcpuid_get_total_cpus\fP (void)" .br .RI "Returns the total number of logical CPU threads (even if CPUID is not present)\&. " .ti -1c .RI "int \fBcpuid_present\fP (void)" .br .RI "Checks if the CPUID instruction is supported\&. " .ti -1c .RI "void \fBcpu_exec_cpuid\fP (uint32_t eax, uint32_t *regs)" .br .RI "Executes the CPUID instruction\&. " .ti -1c .RI "void \fBcpu_exec_cpuid_ext\fP (uint32_t *regs)" .br .RI "Executes the CPUID instruction with the given input registers\&. " .ti -1c .RI "int \fBcpuid_get_raw_data\fP (struct \fBcpu_raw_data_t\fP *data)" .br .RI "Obtains the raw CPUID data from the current CPU\&. " .ti -1c .RI "int \fBcpuid_get_raw_data_core\fP (struct \fBcpu_raw_data_t\fP *data, logical_cpu_t logical_cpu)" .br .RI "Obtains the raw CPUID data from the specified CPU\&. " .ti -1c .RI "int \fBcpuid_get_all_raw_data\fP (struct \fBcpu_raw_data_array_t\fP *data)" .br .RI "Obtains the raw CPUID data from all CPUs\&. " .ti -1c .RI "int \fBcpuid_serialize_raw_data\fP (struct \fBcpu_raw_data_t\fP *data, const char *filename)" .br .RI "Writes the raw CPUID data to a text file\&. " .ti -1c .RI "int \fBcpuid_serialize_all_raw_data\fP (struct \fBcpu_raw_data_array_t\fP *data, const char *filename)" .br .RI "Writes all the raw CPUID data to a text file\&. " .ti -1c .RI "int \fBcpuid_deserialize_raw_data\fP (struct \fBcpu_raw_data_t\fP *data, const char *filename)" .br .RI "Reads raw CPUID data from file\&. " .ti -1c .RI "int \fBcpuid_deserialize_all_raw_data\fP (struct \fBcpu_raw_data_array_t\fP *data, const char *filename)" .br .RI "Reads all raw CPUID data from file\&. " .ti -1c .RI "int \fBcpu_identify\fP (struct \fBcpu_raw_data_t\fP *raw, struct \fBcpu_id_t\fP *data)" .br .RI "Identifies the CPU\&. " .ti -1c .RI "int \fBcpu_identify_all\fP (struct \fBcpu_raw_data_array_t\fP *raw_array, struct \fBsystem_id_t\fP *system)" .br .RI "Identifies all the CPUs\&. " .ti -1c .RI "int \fBcpu_request_core_type\fP (\fBcpu_purpose_t\fP purpose, struct \fBcpu_raw_data_array_t\fP *raw_array, struct \fBcpu_id_t\fP *data)" .br .RI "Identifies a given CPU type\&. " .ti -1c .RI "const char * \fBcpu_architecture_str\fP (\fBcpu_architecture_t\fP architecture)" .br .RI "Returns the short textual representation of a CPU architecture\&. " .ti -1c .RI "const char * \fBcpu_feature_level_str\fP (\fBcpu_feature_level_t\fP level)" .br .RI "Returns the short textual representation of a CPU feature level\&. " .ti -1c .RI "const char * \fBcpu_purpose_str\fP (\fBcpu_purpose_t\fP purpose)" .br .RI "Returns the short textual representation of a CPU purpose\&. " .ti -1c .RI "char * \fBaffinity_mask_str_r\fP (\fBcpu_affinity_mask_t\fP *affinity_mask, char *buffer, uint32_t buffer_len)" .br .RI "Returns textual representation of a CPU affinity mask (thread-safe) " .ti -1c .RI "char * \fBaffinity_mask_str\fP (\fBcpu_affinity_mask_t\fP *affinity_mask)" .br .RI "Returns textual representation of a CPU affinity mask\&. " .ti -1c .RI "const char * \fBcpu_feature_str\fP (\fBcpu_feature_t\fP feature)" .br .RI "Returns the short textual representation of a CPU flag\&. " .ti -1c .RI "const char * \fBcpuid_error\fP (void)" .br .RI "Returns textual description of the last error\&. " .ti -1c .RI "void \fBcpu_rdtsc\fP (uint64_t *result)" .br .RI "Executes RDTSC\&. " .ti -1c .RI "void \fBcpu_tsc_mark\fP (struct \fBcpu_mark_t\fP *mark)" .br .RI "Store TSC and timing info\&. " .ti -1c .RI "void \fBcpu_tsc_unmark\fP (struct \fBcpu_mark_t\fP *mark)" .br .RI "Calculate TSC and timing difference\&. " .ti -1c .RI "int \fBcpu_clock_by_mark\fP (struct \fBcpu_mark_t\fP *mark)" .br .RI "Calculates the CPU clock\&. " .ti -1c .RI "int \fBcpu_clock_by_os\fP (void)" .br .RI "Returns the CPU clock, as reported by the OS\&. " .ti -1c .RI "int \fBcpu_clock_measure\fP (int millis, int quad_check)" .br .RI "Measure the CPU clock frequency\&. " .ti -1c .RI "int \fBcpu_clock_by_ic\fP (int millis, int runs)" .br .RI "Measure the CPU clock frequency using instruction-counting\&. " .ti -1c .RI "int \fBcpu_clock_by_tsc\fP (struct \fBcpu_raw_data_t\fP *raw)" .br .RI "Measure the CPU clock frequency using TSC frequency from CPUID\&. " .ti -1c .RI "int \fBcpu_clock\fP (void)" .br .RI "Get the CPU clock frequency (all-in-one method) " .ti -1c .RI "struct \fBcpu_epc_t\fP \fBcpuid_get_epc\fP (int index, const struct \fBcpu_raw_data_t\fP *raw)" .br .RI "Fetches information about an EPC (Enclave Page Cache) area\&. " .ti -1c .RI "const char * \fBcpuid_lib_version\fP (void)" .br .RI "Returns the libcpuid version\&. " .ti -1c .RI "libcpuid_warn_fn_t \fBcpuid_set_warn_function\fP (libcpuid_warn_fn_t warn_fun)" .br .RI "Sets the warning print function\&. " .ti -1c .RI "void \fBcpuid_set_verbosiness_level\fP (int level)" .br .RI "Sets the verbosiness level\&. " .ti -1c .RI "\fBcpu_vendor_t\fP \fBcpuid_get_vendor\fP (void)" .br .RI "Obtains the CPU vendor from CPUID from the current CPU\&. " .ti -1c .RI "\fBhypervisor_vendor_t\fP \fBcpuid_get_hypervisor\fP (struct \fBcpu_raw_data_t\fP *raw, struct \fBcpu_id_t\fP *data)" .br .RI "Obtains the hypervisor vendor from CPUID from the current CPU\&. " .ti -1c .RI "void \fBcpuid_get_cpu_list\fP (\fBcpu_vendor_t\fP vendor, struct \fBcpu_list_t\fP *list)" .br .RI "Gets a list of all known CPU names from a specific vendor\&. " .ti -1c .RI "void \fBcpuid_free_cpu_list\fP (struct \fBcpu_list_t\fP *list)" .br .RI "Frees a CPU list\&. " .ti -1c .RI "void \fBcpuid_free_raw_data_array\fP (struct \fBcpu_raw_data_array_t\fP *raw_array)" .br .RI "Frees a raw array\&. " .ti -1c .RI "void \fBcpuid_free_system_id\fP (struct \fBsystem_id_t\fP *system)" .br .RI "Frees a system ID type\&. " .ti -1c .RI "struct msr_driver_t * \fBcpu_msr_driver_open\fP (void)" .br .RI "Starts/opens a driver, needed to read MSRs (Model Specific Registers) " .ti -1c .RI "struct msr_driver_t * \fBcpu_msr_driver_open_core\fP (unsigned core_num)" .br .RI "Similar to \fBcpu_msr_driver_open\fP, but accept one parameter\&. " .ti -1c .RI "int \fBcpu_rdmsr\fP (struct msr_driver_t *handle, uint32_t msr_index, uint64_t *result)" .br .RI "Reads a Model-Specific Register (MSR) " .ti -1c .RI "int \fBcpu_rdmsr_range\fP (struct msr_driver_t *handle, uint32_t msr_index, uint8_t highbit, uint8_t lowbit, uint64_t *result)" .br .RI "Similar to \fBcpu_rdmsr\fP, but extract a range of bits\&. " .ti -1c .RI "int \fBcpu_msrinfo\fP (struct msr_driver_t *handle, \fBcpu_msrinfo_request_t\fP which)" .br .RI "Reads extended CPU information from Model-Specific Registers\&. " .ti -1c .RI "int \fBmsr_serialize_raw_data\fP (struct msr_driver_t *handle, const char *filename)" .br .RI "Writes the raw MSR data to a text file\&. " .ti -1c .RI "int \fBcpu_msr_driver_close\fP (struct msr_driver_t *handle)" .br .RI "Closes an open MSR driver\&. " .in -1c .SH "Detailed Description" .PP LibCPUID provides CPU identification\&. .SH "Enumeration Type Documentation" .PP .SS "enum \fBcpu_architecture_t\fP" .PP CPU architecture\&. .PP \fBEnumerator\fP .in +1c .TP \f(BIARCHITECTURE_X86 \fP x86 CPU .TP \f(BIARCHITECTURE_ARM \fP ARM CPU .TP \f(BINUM_CPU_ARCHITECTURES \fP Valid CPU architecture ids: 0\&.\&.NUM_CPU_ARCHITECTURES - 1 .SS "enum \fBcpu_error_t\fP" .PP Describes common library error codes\&. .PP \fBEnumerator\fP .in +1c .TP \f(BIERR_OK \fP No error .TP \f(BIERR_NO_CPUID \fP CPUID instruction is not supported .TP \f(BIERR_NO_RDTSC \fP RDTSC instruction is not supported .TP \f(BIERR_NO_MEM \fP Memory allocation failed .TP \f(BIERR_OPEN \fP File open operation failed .TP \f(BIERR_BADFMT \fP Bad file format .TP \f(BIERR_NOT_IMP \fP Not implemented .TP \f(BIERR_CPU_UNKN \fP Unsupported processor .TP \f(BIERR_NO_RDMSR \fP RDMSR instruction is not supported .TP \f(BIERR_NO_DRIVER \fP RDMSR driver error (generic) .TP \f(BIERR_NO_PERMS \fP No permissions to install RDMSR driver .TP \f(BIERR_EXTRACT \fP Cannot extract RDMSR driver (read only media?) .TP \f(BIERR_HANDLE \fP Bad handle .TP \f(BIERR_INVMSR \fP Invalid MSR .TP \f(BIERR_INVCNB \fP Invalid core number .TP \f(BIERR_HANDLE_R \fP Error on handle read .TP \f(BIERR_INVRANGE \fP Invalid given range .TP \f(BIERR_NOT_FOUND \fP Requested type not found .TP \f(BIERR_IOCTL \fP Error on ioctl .TP \f(BIERR_REQUEST \fP Invalid request .SS "enum \fBcpu_feature_level_t\fP" .PP CPU feature level\&. .PP \fBEnumerator\fP .in +1c .TP \f(BIFEATURE_LEVEL_I386 \fP i386 .TP \f(BIFEATURE_LEVEL_I486 \fP i486 .TP \f(BIFEATURE_LEVEL_I586 \fP i586 .TP \f(BIFEATURE_LEVEL_I686 \fP i686 .TP \f(BIFEATURE_LEVEL_X86_64_V1 \fP x86-64-v1 .TP \f(BIFEATURE_LEVEL_X86_64_V2 \fP x86-64-v2 .TP \f(BIFEATURE_LEVEL_X86_64_V3 \fP x86-64-v3 .TP \f(BIFEATURE_LEVEL_X86_64_V4 \fP x86-64-v4 .TP \f(BIFEATURE_LEVEL_ARM_V1 \fP ARMv1 .TP \f(BIFEATURE_LEVEL_ARM_V2 \fP ARMv2 .TP \f(BIFEATURE_LEVEL_ARM_V3 \fP ARMv3 .TP \f(BIFEATURE_LEVEL_ARM_V4 \fP ARMv4 .TP \f(BIFEATURE_LEVEL_ARM_V4T \fP ARMv4T .TP \f(BIFEATURE_LEVEL_ARM_V5 \fP ARMv5 (obsolete) .TP \f(BIFEATURE_LEVEL_ARM_V5T \fP ARMv5T .TP \f(BIFEATURE_LEVEL_ARM_V5TE \fP ARMv5TE .TP \f(BIFEATURE_LEVEL_ARM_V5TEJ \fP ARMv5TEJ .TP \f(BIFEATURE_LEVEL_ARM_V6 \fP ARMv6 .TP \f(BIFEATURE_LEVEL_ARM_V6_M \fP ARMv6-M .TP \f(BIFEATURE_LEVEL_ARM_V7_A \fP ARMv7-A .TP \f(BIFEATURE_LEVEL_ARM_V7_M \fP ARMv7-M .TP \f(BIFEATURE_LEVEL_ARM_V7_R \fP ARMv7-R .TP \f(BIFEATURE_LEVEL_ARM_V7E_M \fP ARMv7E-M .TP \f(BIFEATURE_LEVEL_ARM_V8_0_A \fP ARMv8\&.0-A .TP \f(BIFEATURE_LEVEL_ARM_V8_0_M \fP ARMv8\&.0-M .TP \f(BIFEATURE_LEVEL_ARM_V8_0_R \fP ARMv8\&.0-R .TP \f(BIFEATURE_LEVEL_ARM_V8_1_A \fP ARMv8\&.1-A .TP \f(BIFEATURE_LEVEL_ARM_V8_1_M \fP ARMv8\&.1-M .TP \f(BIFEATURE_LEVEL_ARM_V8_2_A \fP ARMv8\&.2-A .TP \f(BIFEATURE_LEVEL_ARM_V8_3_A \fP ARMv8\&.3-A .TP \f(BIFEATURE_LEVEL_ARM_V8_4_A \fP ARMv8\&.4-A .TP \f(BIFEATURE_LEVEL_ARM_V8_5_A \fP ARMv8\&.5-A .TP \f(BIFEATURE_LEVEL_ARM_V8_6_A \fP ARMv8\&.6-A .TP \f(BIFEATURE_LEVEL_ARM_V8_7_A \fP ARMv8\&.7-A .TP \f(BIFEATURE_LEVEL_ARM_V8_8_A \fP ARMv8\&.8-A .TP \f(BIFEATURE_LEVEL_ARM_V8_9_A \fP ARMv8\&.9-A .TP \f(BIFEATURE_LEVEL_ARM_V9_0_A \fP ARMv9\&.0-A .TP \f(BIFEATURE_LEVEL_ARM_V9_1_A \fP ARMv9\&.1-A .TP \f(BIFEATURE_LEVEL_ARM_V9_2_A \fP ARMv9\&.2-A .TP \f(BIFEATURE_LEVEL_ARM_V9_3_A \fP ARMv9\&.3-A .TP \f(BIFEATURE_LEVEL_ARM_V9_4_A \fP ARMv9\&.4-A .TP \f(BIFEATURE_LEVEL_ARM_V9_5_A \fP ARMv9\&.5-A .TP \f(BINUM_FEATURE_LEVELS \fP Valid feature level ids: 0\&.\&.NUM_FEATURE_LEVELS - 1 .SS "enum \fBcpu_feature_t\fP" .PP CPU feature identifiers\&. Usage: .PP .nf \&.\&.\&. struct cpu_raw_data_t raw; struct cpu_id_t id; if (cpuid_get_raw_data(&raw) == 0 && cpu_identify(&raw, &id) == 0) { if (id\&.flags[CPU_FEATURE_SSE2]) { // The CPU has SSE2\&.\&.\&. \&.\&.\&. } else { // no SSE2 } } else { // processor cannot be determined\&. } .fi .PP .PP \fBEnumerator\fP .in +1c .TP \f(BICPU_FEATURE_FPU \fP Floating point unit .TP \f(BICPU_FEATURE_VME \fP Virtual mode extension .TP \f(BICPU_FEATURE_DE \fP Debugging extension .TP \f(BICPU_FEATURE_PSE \fP Page size extension .TP \f(BICPU_FEATURE_TSC \fP Time-stamp counter .TP \f(BICPU_FEATURE_MSR \fP Model-specific regsisters, RDMSR/WRMSR supported .TP \f(BICPU_FEATURE_PAE \fP Physical address extension .TP \f(BICPU_FEATURE_MCE \fP Machine check exception .TP \f(BICPU_FEATURE_CX8 \fP CMPXCHG8B instruction supported .TP \f(BICPU_FEATURE_APIC \fP APIC support .TP \f(BICPU_FEATURE_MTRR \fP Memory type range registers .TP \f(BICPU_FEATURE_SEP \fP SYSENTER / SYSEXIT instructions supported .TP \f(BICPU_FEATURE_PGE \fP Page global enable .TP \f(BICPU_FEATURE_MCA \fP Machine check architecture .TP \f(BICPU_FEATURE_CMOV \fP CMOVxx instructions supported .TP \f(BICPU_FEATURE_PAT \fP Page attribute table .TP \f(BICPU_FEATURE_PSE36 \fP 36-bit page address extension .TP \f(BICPU_FEATURE_PN \fP Processor serial # implemented (Intel P3 only) .TP \f(BICPU_FEATURE_CLFLUSH \fP CLFLUSH instruction supported .TP \f(BICPU_FEATURE_DTS \fP Debug store supported .TP \f(BICPU_FEATURE_ACPI \fP ACPI support (power states) .TP \f(BICPU_FEATURE_MMX \fP MMX instruction set supported .TP \f(BICPU_FEATURE_FXSR \fP FXSAVE / FXRSTOR supported .TP \f(BICPU_FEATURE_SSE \fP Streaming-SIMD Extensions (SSE) supported .TP \f(BICPU_FEATURE_SSE2 \fP SSE2 instructions supported .TP \f(BICPU_FEATURE_SS \fP Self-snoop .TP \f(BICPU_FEATURE_HT \fP Hyper-threading supported (but might be disabled) .TP \f(BICPU_FEATURE_TM \fP Thermal monitor .TP \f(BICPU_FEATURE_IA64 \fP IA64 supported (Itanium only) .TP \f(BICPU_FEATURE_PBE \fP Pending-break enable .TP \f(BICPU_FEATURE_PNI \fP PNI (SSE3) instructions supported .TP \f(BICPU_FEATURE_PCLMUL \fP PCLMULQDQ instruction supported .TP \f(BICPU_FEATURE_DTS64 \fP 64-bit Debug store supported .TP \f(BICPU_FEATURE_MONITOR \fP MONITOR / MWAIT supported .TP \f(BICPU_FEATURE_DS_CPL \fP CPL Qualified Debug Store .TP \f(BICPU_FEATURE_VMX \fP Virtualization technology supported .TP \f(BICPU_FEATURE_SMX \fP Safer mode exceptions .TP \f(BICPU_FEATURE_EST \fP Enhanced SpeedStep .TP \f(BICPU_FEATURE_TM2 \fP Thermal monitor 2 .TP \f(BICPU_FEATURE_SSSE3 \fP SSSE3 instructionss supported (this is different from SSE3!) .TP \f(BICPU_FEATURE_CID \fP Context ID supported .TP \f(BICPU_FEATURE_CX16 \fP CMPXCHG16B instruction supported .TP \f(BICPU_FEATURE_XTPR \fP Send Task Priority Messages disable .TP \f(BICPU_FEATURE_PDCM \fP Performance capabilities MSR supported .TP \f(BICPU_FEATURE_DCA \fP Direct cache access supported .TP \f(BICPU_FEATURE_SSE4_1 \fP SSE 4\&.1 instructions supported .TP \f(BICPU_FEATURE_SSE4_2 \fP SSE 4\&.2 instructions supported .TP \f(BICPU_FEATURE_SYSCALL \fP SYSCALL / SYSRET instructions supported .TP \f(BICPU_FEATURE_XD \fP Execute disable bit supported .TP \f(BICPU_FEATURE_MOVBE \fP MOVBE instruction supported .TP \f(BICPU_FEATURE_POPCNT \fP POPCNT instruction supported .TP \f(BICPU_FEATURE_AES \fP AES* instructions supported .TP \f(BICPU_FEATURE_XSAVE \fP XSAVE/XRSTOR/etc instructions supported .TP \f(BICPU_FEATURE_OSXSAVE \fP non-privileged copy of OSXSAVE supported .TP \f(BICPU_FEATURE_AVX \fP Advanced vector extensions supported .TP \f(BICPU_FEATURE_MMXEXT \fP AMD MMX-extended instructions supported .TP \f(BICPU_FEATURE_3DNOW \fP AMD 3DNow! instructions supported .TP \f(BICPU_FEATURE_3DNOWEXT \fP AMD 3DNow! extended instructions supported .TP \f(BICPU_FEATURE_NX \fP No-execute bit supported .TP \f(BICPU_FEATURE_FXSR_OPT \fP FFXSR: FXSAVE and FXRSTOR optimizations .TP \f(BICPU_FEATURE_RDTSCP \fP RDTSCP instruction supported (AMD-only) .TP \f(BICPU_FEATURE_LM \fP Long mode (x86_64/EM64T) supported .TP \f(BICPU_FEATURE_LAHF_LM \fP LAHF/SAHF supported in 64-bit mode .TP \f(BICPU_FEATURE_CMP_LEGACY \fP core multi-processing legacy mode .TP \f(BICPU_FEATURE_SVM \fP AMD Secure virtual machine .TP \f(BICPU_FEATURE_ABM \fP LZCNT instruction support .TP \f(BICPU_FEATURE_MISALIGNSSE \fP Misaligned SSE supported .TP \f(BICPU_FEATURE_SSE4A \fP SSE 4a from AMD .TP \f(BICPU_FEATURE_3DNOWPREFETCH \fP PREFETCH/PREFETCHW support .TP \f(BICPU_FEATURE_OSVW \fP OS Visible Workaround (AMD) .TP \f(BICPU_FEATURE_IBS \fP Instruction-based sampling .TP \f(BICPU_FEATURE_SSE5 \fP SSE 5 instructions supported (deprecated, will never be 1) .TP \f(BICPU_FEATURE_SKINIT \fP SKINIT / STGI supported .TP \f(BICPU_FEATURE_WDT \fP Watchdog timer support .TP \f(BICPU_FEATURE_TS \fP Temperature sensor .TP \f(BICPU_FEATURE_FID \fP Frequency ID control .TP \f(BICPU_FEATURE_VID \fP Voltage ID control .TP \f(BICPU_FEATURE_TTP \fP THERMTRIP .TP \f(BICPU_FEATURE_TM_AMD \fP AMD-specified hardware thermal control .TP \f(BICPU_FEATURE_STC \fP Software thermal control .TP \f(BICPU_FEATURE_100MHZSTEPS \fP 100 MHz multiplier control .TP \f(BICPU_FEATURE_HWPSTATE \fP Hardware P-state control .TP \f(BICPU_FEATURE_CONSTANT_TSC \fP TSC ticks at constant rate .TP \f(BICPU_FEATURE_XOP \fP The XOP instruction set (same as the old CPU_FEATURE_SSE5) .TP \f(BICPU_FEATURE_FMA3 \fP The FMA3 instruction set .TP \f(BICPU_FEATURE_FMA4 \fP The FMA4 instruction set .TP \f(BICPU_FEATURE_TBM \fP Trailing bit manipulation instruction support .TP \f(BICPU_FEATURE_F16C \fP 16-bit FP convert instruction support .TP \f(BICPU_FEATURE_RDRAND \fP RdRand instruction .TP \f(BICPU_FEATURE_X2APIC \fP x2APIC, APIC_BASE\&.EXTD, MSRs 0000_0800h\&.\&.\&.0000_0BFFh 64-bit ICR (+030h but not +031h), no DFR (+00Eh), SELF_IPI (+040h) also see standard level 0000_000Bh .TP \f(BICPU_FEATURE_CPB \fP Core performance boost .TP \f(BICPU_FEATURE_APERFMPERF \fP MPERF/APERF MSRs support .TP \f(BICPU_FEATURE_PFI \fP Processor Feedback Interface support .TP \f(BICPU_FEATURE_PA \fP Processor accumulator .TP \f(BICPU_FEATURE_AVX2 \fP AVX2 instructions .TP \f(BICPU_FEATURE_BMI1 \fP BMI1 instructions .TP \f(BICPU_FEATURE_BMI2 \fP BMI2 instructions .TP \f(BICPU_FEATURE_HLE \fP Hardware Lock Elision prefixes .TP \f(BICPU_FEATURE_RTM \fP Restricted Transactional Memory instructions .TP \f(BICPU_FEATURE_AVX512F \fP AVX-512 Foundation .TP \f(BICPU_FEATURE_AVX512DQ \fP AVX-512 Double/Quad granular insns .TP \f(BICPU_FEATURE_AVX512PF \fP AVX-512 Prefetch .TP \f(BICPU_FEATURE_AVX512ER \fP AVX-512 Exponential/Reciprocal .TP \f(BICPU_FEATURE_AVX512CD \fP AVX-512 Conflict detection .TP \f(BICPU_FEATURE_SHA_NI \fP SHA-1/SHA-256 instructions .TP \f(BICPU_FEATURE_AVX512BW \fP AVX-512 Byte/Word granular insns .TP \f(BICPU_FEATURE_AVX512VL \fP AVX-512 128/256 vector length extensions .TP \f(BICPU_FEATURE_SGX \fP SGX extensions\&. Non-autoritative, check cpu_id_t::sgx::present to verify presence .TP \f(BICPU_FEATURE_RDSEED \fP RDSEED instruction .TP \f(BICPU_FEATURE_ADX \fP ADX extensions (arbitrary precision) .TP \f(BICPU_FEATURE_AVX512VNNI \fP AVX-512 Vector Neural Network Instructions .TP \f(BICPU_FEATURE_AVX512VBMI \fP AVX-512 Vector Bit ManipulationInstructions (version 1) .TP \f(BICPU_FEATURE_AVX512VBMI2 \fP AVX-512 Vector Bit ManipulationInstructions (version 2) .TP \f(BICPU_FEATURE_HYPERVISOR \fP Hypervisor present (always zero on physical CPUs) .TP \f(BICPU_FEATURE_SWAP \fP ARM: Swap instructions in the ARM instruction set .TP \f(BICPU_FEATURE_THUMB \fP ARM: Thumb instruction set support .TP \f(BICPU_FEATURE_ADVMULTU \fP ARM: Advanced unsigned Multiply instructions .TP \f(BICPU_FEATURE_ADVMULTS \fP ARM: Advanced signed Multiply instructions .TP \f(BICPU_FEATURE_JAZELLE \fP ARM: Jazelle extension support .TP \f(BICPU_FEATURE_DEBUGV6 \fP ARM: Support for v6 Debug architecture .TP \f(BICPU_FEATURE_DEBUGV6P1 \fP ARM: Support for v6\&.1 Debug architecture .TP \f(BICPU_FEATURE_THUMB2 \fP ARM: Thumb-2, instruction set support .TP \f(BICPU_FEATURE_DEBUGV7 \fP ARM: Support for v7 Debug architecture .TP \f(BICPU_FEATURE_DEBUGV7P1 \fP ARM: Support for v7\&.1 Debug architecture .TP \f(BICPU_FEATURE_THUMBEE \fP ARM: ThumbEE instruction set support .TP \f(BICPU_FEATURE_DIVIDE \fP ARM: Divide instructions .TP \f(BICPU_FEATURE_LPAE \fP ARM: Large Physical Address Extension .TP \f(BICPU_FEATURE_PMUV1 \fP ARM: PMU extension version 1 .TP \f(BICPU_FEATURE_PMUV2 \fP ARM: PMU extension version 2 .TP \f(BICPU_FEATURE_ASID16 \fP ARM: 16 bit ASID .TP \f(BICPU_FEATURE_ADVSIMD \fP ARM: Advanced SIMD Extension .TP \f(BICPU_FEATURE_CRC32 \fP ARM: CRC32 instructions .TP \f(BICPU_FEATURE_CSV2_1P1 \fP ARM: Cache Speculation Variant 2 .TP \f(BICPU_FEATURE_CSV2_1P2 \fP ARM: Cache Speculation Variant 2 version 1\&.2 .TP \f(BICPU_FEATURE_CSV2_2 \fP ARM: Cache Speculation Variant 2 version 2 .TP \f(BICPU_FEATURE_CSV2_3 \fP ARM: Cache Speculation Variant 2 version 3 .TP \f(BICPU_FEATURE_DOUBLELOCK \fP ARM: Double Lock .TP \f(BICPU_FEATURE_ETS2 \fP ARM: Enhanced Translation Synchronization .TP \f(BICPU_FEATURE_FP \fP ARM: Floating Point extensions .TP \f(BICPU_FEATURE_MIXEDEND \fP ARM: Mixed-endian support .TP \f(BICPU_FEATURE_MIXEDENDEL0 \fP ARM: Mixed-endian support at EL0 .TP \f(BICPU_FEATURE_PMULL \fP ARM: Advanced SIMD PMULL instructions .TP \f(BICPU_FEATURE_PMUV3 \fP ARM: PMU extension version 3 .TP \f(BICPU_FEATURE_SHA1 \fP ARM: Advanced SIMD SHA1 instructions .TP \f(BICPU_FEATURE_SHA256 \fP ARM: Advanced SIMD SHA256 instructions .TP \f(BICPU_FEATURE_NTLBPA \fP ARM: Intermediate caching of translation table walks .TP \f(BICPU_FEATURE_HAFDBS \fP ARM: Hardware management of the Access flag and dirty state .TP \f(BICPU_FEATURE_HPDS \fP ARM: Hierarchical permission disables in translations tables .TP \f(BICPU_FEATURE_LOR \fP ARM: Limited ordering regions .TP \f(BICPU_FEATURE_LSE \fP ARM: Large System Extensions .TP \f(BICPU_FEATURE_PAN \fP ARM: Privileged access never .TP \f(BICPU_FEATURE_PMUV3P1 \fP ARM: Armv8\&.1 PMU extensions .TP \f(BICPU_FEATURE_RDM \fP ARM: Advanced SIMD rounding double multiply accumulate instructions .TP \f(BICPU_FEATURE_VHE \fP ARM: Virtualization Host Extensions .TP \f(BICPU_FEATURE_VMID16 \fP ARM: 16-bit VMID .TP \f(BICPU_FEATURE_AA32HPD \fP ARM: AArch32 Hierarchical permission disables .TP \f(BICPU_FEATURE_AA32I8MM \fP ARM: AArch32 Int8 matrix multiplication instructions .TP \f(BICPU_FEATURE_DPB \fP ARM: DC CVAP instruction .TP \f(BICPU_FEATURE_DEBUGV8P2 \fP ARM: Debug v8\&.2 .TP \f(BICPU_FEATURE_F32MM \fP ARM: Single-precision Matrix Multiplication .TP \f(BICPU_FEATURE_F64MM \fP ARM: Double-precision Matrix Multiplication .TP \f(BICPU_FEATURE_FP16 \fP ARM: Half-precision floating-point data processing .TP \f(BICPU_FEATURE_HPDS2 \fP ARM: Hierarchical permission disables .TP \f(BICPU_FEATURE_I8MM \fP ARM: AArch64 Int8 matrix multiplication instructions .TP \f(BICPU_FEATURE_IESB \fP ARM: Implicit Error Synchronization event .TP \f(BICPU_FEATURE_LPA \fP ARM: Large PA and IPA support .TP \f(BICPU_FEATURE_LSMAOC \fP ARM: AArch32 Load/Store Multiple instruction atomicity and ordering controls .TP \f(BICPU_FEATURE_LVA \fP ARM: Large VA support .TP \f(BICPU_FEATURE_PAN2 \fP ARM: AT S1E1R and AT S1E1W instruction variants affected by PSTATE\&.PAN .TP \f(BICPU_FEATURE_RAS \fP ARM: Reliability, Availability and Serviceability (RAS) Extension .TP \f(BICPU_FEATURE_SHA3 \fP ARM: Advanced SIMD SHA3 instructions .TP \f(BICPU_FEATURE_SHA512 \fP ARM: Advanced SIMD SHA512 instructions .TP \f(BICPU_FEATURE_SM3 \fP ARM: Advanced SIMD SM3 instructions .TP \f(BICPU_FEATURE_SM4 \fP ARM: Advanced SIMD SM4 instructions .TP \f(BICPU_FEATURE_SPE \fP ARM: Statistical Profiling Extension .TP \f(BICPU_FEATURE_SVE \fP ARM: Scalable Vector Extension .TP \f(BICPU_FEATURE_TTCNP \fP ARM: Translation table Common not private translations .TP \f(BICPU_FEATURE_UAO \fP ARM: Unprivileged Access Override control .TP \f(BICPU_FEATURE_XNX \fP ARM: Translation table stage 2 Unprivileged Execute-never .TP \f(BICPU_FEATURE_CCIDX \fP ARM: Extended cache index .TP \f(BICPU_FEATURE_CONSTPACFIELD \fP ARM: PAC algorithm enhancement .TP \f(BICPU_FEATURE_EPAC \fP ARM: Enhanced pointer authentication .TP \f(BICPU_FEATURE_FCMA \fP ARM: Floating-point complex number instructions .TP \f(BICPU_FEATURE_FPAC \fP ARM: Faulting on AUT* instructions .TP \f(BICPU_FEATURE_FPACCOMBINE \fP ARM: Faulting on combined pointer authentication instructions .TP \f(BICPU_FEATURE_JSCVT \fP ARM: JavaScript conversion instructions .TP \f(BICPU_FEATURE_LRCPC \fP ARM: Load-Acquire RCpc instructions .TP \f(BICPU_FEATURE_PACIMP \fP ARM: Pointer authentication - IMPLEMENTATION DEFINED algorithm .TP \f(BICPU_FEATURE_PACQARMA3 \fP ARM: Pointer authentication - QARMA3 algorithm .TP \f(BICPU_FEATURE_PACQARMA5 \fP ARM: Pointer authentication - QARMA5 algorithm .TP \f(BICPU_FEATURE_PAUTH \fP ARM: Pointer authentication .TP \f(BICPU_FEATURE_SPEV1P1 \fP ARM: Statistical Profiling Extension version 1 .TP \f(BICPU_FEATURE_AMUV1 \fP ARM: Activity Monitors Extension version 1 .TP \f(BICPU_FEATURE_BBM \fP ARM: Translation table break-before-make levels .TP \f(BICPU_FEATURE_DIT \fP ARM: Data Independent Timing instructions .TP \f(BICPU_FEATURE_DEBUGV8P4 \fP ARM: Debug v8\&.4 .TP \f(BICPU_FEATURE_DOTPROD \fP ARM: Advanced SIMD dot product instructions .TP \f(BICPU_FEATURE_DOUBLEFAULT \fP ARM: Double Fault Extension .TP \f(BICPU_FEATURE_FHM \fP ARM: Floating-point half-precision to single-precision multiply-add instructions .TP \f(BICPU_FEATURE_FLAGM \fP ARM: Condition flag manipulation instructions .TP \f(BICPU_FEATURE_IDST \fP ARM: ID space trap handling .TP \f(BICPU_FEATURE_LRCPC2 \fP ARM: Load-Acquire RCpc instructions version 2 .TP \f(BICPU_FEATURE_LSE2 \fP ARM: Large System Extensions version 2 .TP \f(BICPU_FEATURE_MPAM \fP ARM: Memory Partitioning and Monitoring Extension .TP \f(BICPU_FEATURE_PMUV3P4 \fP ARM: Arm8\&.4 PMU extensions .TP \f(BICPU_FEATURE_RASV1P1 \fP ARM: RAS extension v1\&.1 .TP \f(BICPU_FEATURE_S2FWB \fP ARM: Stage 2 forced Write-Back .TP \f(BICPU_FEATURE_SEL2 \fP ARM: Secure EL2 .TP \f(BICPU_FEATURE_TLBIOS \fP ARM: TLB invalidate instructions in Outer Shareable domain .TP \f(BICPU_FEATURE_TLBIRANGE \fP ARM: TLB invalidate range instructions .TP \f(BICPU_FEATURE_TRF \fP ARM: Self-hosted Trace extensions .TP \f(BICPU_FEATURE_TTL \fP ARM: Translation Table Level .TP \f(BICPU_FEATURE_TTST \fP ARM: Small translation tables .TP \f(BICPU_FEATURE_BTI \fP ARM: Branch Target Identification .TP \f(BICPU_FEATURE_CSV2 \fP ARM: Cache Speculation Variant 2 .TP \f(BICPU_FEATURE_CSV3 \fP ARM: Cache Speculation Variant 3 .TP \f(BICPU_FEATURE_DPB2 \fP ARM: DC CVADP instruction .TP \f(BICPU_FEATURE_E0PD \fP ARM: Preventing EL0 access to halves of address maps .TP \f(BICPU_FEATURE_EVT \fP ARM: Enhanced Virtualization Traps .TP \f(BICPU_FEATURE_EXS \fP ARM: Context synchronization and exception handling .TP \f(BICPU_FEATURE_FRINTTS \fP ARM: Floating-point to integer instructions .TP \f(BICPU_FEATURE_FLAGM2 \fP ARM: Enhancements to flag manipulation instructions .TP \f(BICPU_FEATURE_MTE \fP ARM: Memory Tagging Extension .TP \f(BICPU_FEATURE_MTE2 \fP ARM: Memory Tagging Extension .TP \f(BICPU_FEATURE_PMUV3P5 \fP ARM: Arm8\&.5 PMU extensions .TP \f(BICPU_FEATURE_RNG \fP ARM: Random number generator .TP \f(BICPU_FEATURE_RNG_TRAP \fP ARM: Trapping support for RNDR/RNDRRS .TP \f(BICPU_FEATURE_SB \fP ARM: Speculation Barrier .TP \f(BICPU_FEATURE_SPECRES \fP ARM: Speculation restriction instructions .TP \f(BICPU_FEATURE_SSBS \fP ARM: Speculative Store Bypass Safe .TP \f(BICPU_FEATURE_SSBS2 \fP ARM: MRS and MSR instructions for SSBS version 2 .TP \f(BICPU_FEATURE_AA32BF16 \fP ARM: AArch32 BFloat16 instructions .TP \f(BICPU_FEATURE_AMUV1P1 \fP ARM: Activity Monitors Extension version 1\&.1 .TP \f(BICPU_FEATURE_BF16 \fP ARM: AArch64 BFloat16 instructions .TP \f(BICPU_FEATURE_DGH \fP ARM: Data Gathering Hint .TP \f(BICPU_FEATURE_ECV \fP ARM: Enhanced Counter Virtualization .TP \f(BICPU_FEATURE_FGT \fP ARM: Fine Grain Traps .TP \f(BICPU_FEATURE_HPMN0 \fP ARM: Setting of MDCR_EL2\&.HPMN to zero .TP \f(BICPU_FEATURE_MPAMV0P1 \fP ARM: Memory Partitioning and Monitoring extension version 0\&.1 .TP \f(BICPU_FEATURE_MPAMV1P1 \fP ARM: Memory Partitioning and Monitoring extension version 1\&.1 .TP \f(BICPU_FEATURE_MTPMU \fP ARM: Multi-threaded PMU extensions .TP \f(BICPU_FEATURE_PAUTH2 \fP ARM: Enhancements to pointer authentication .TP \f(BICPU_FEATURE_TWED \fP ARM: Delayed Trapping of WFE .TP \f(BICPU_FEATURE_AFP \fP ARM: Alternate floating-point behavior .TP \f(BICPU_FEATURE_EBF16 \fP ARM: AArch64 Extended BFloat16 behaviors .TP \f(BICPU_FEATURE_HCX \fP ARM: Support for the HCRX_EL2 register .TP \f(BICPU_FEATURE_LPA2 \fP ARM: Larger physical address for 4KB and 16KB translation granules .TP \f(BICPU_FEATURE_LS64 \fP ARM: Support for 64-byte loads and stores without status .TP \f(BICPU_FEATURE_LS64_ACCDATA \fP ARM: Support for 64-byte EL0 stores with status .TP \f(BICPU_FEATURE_LS64_V \fP ARM: Support for 64-byte stores with status .TP \f(BICPU_FEATURE_MTE3 \fP ARM: MTE Asymmetric Fault Handling .TP \f(BICPU_FEATURE_MTE_ASYM_FAULT \fP ARM: Memory tagging asymmetric faults .TP \f(BICPU_FEATURE_PAN3 \fP ARM: Support for SCTLR_ELx\&.EPAN .TP \f(BICPU_FEATURE_PMUV3P7 \fP ARM: Armv8\&.7 PMU extensions .TP \f(BICPU_FEATURE_RPRES \fP ARM: Increased precision of FRECPE and FRSQRTE .TP \f(BICPU_FEATURE_SPEV1P2 \fP ARM: Statistical Profiling Extensions version 1\&.2 .TP \f(BICPU_FEATURE_WFXT \fP ARM: WFE and WFI instructions with timeout .TP \f(BICPU_FEATURE_XS \fP ARM: XS attribute .TP \f(BICPU_FEATURE_CMOW \fP ARM: Control for cache maintenance permission .TP \f(BICPU_FEATURE_DEBUGV8P8 \fP ARM: Debug v8\&.8 .TP \f(BICPU_FEATURE_HBC \fP ARM: Hinted conditional branches .TP \f(BICPU_FEATURE_MOPS \fP ARM: Standardization of memory operations .TP \f(BICPU_FEATURE_NMI \fP ARM: Non-maskable Interrupts .TP \f(BICPU_FEATURE_PMUV3P8 \fP ARM: Armv8\&.8 PMU extensions .TP \f(BICPU_FEATURE_SCTLR2 \fP ARM: Extension to SCTLR_ELx .TP \f(BICPU_FEATURE_SPEV1P3 \fP ARM: Statistical Profiling Extensions version 1\&.3 .TP \f(BICPU_FEATURE_TCR2 \fP ARM: Support for TCR2_ELx .TP \f(BICPU_FEATURE_TIDCP1 \fP ARM: EL0 use of IMPLEMENTATION DEFINED functionality .TP \f(BICPU_FEATURE_ADERR \fP ARM: Asynchronous Device Error Exceptions .TP \f(BICPU_FEATURE_AIE \fP ARM: Memory Attribute Index Enhancement .TP \f(BICPU_FEATURE_ANERR \fP ARM: Asynchronous Normal Error Exceptions .TP \f(BICPU_FEATURE_ATS1A \fP ARM: Address Translation operations that ignore stage 1 permissions .TP \f(BICPU_FEATURE_CLRBHB \fP ARM: Support for Clear Branch History instruction .TP \f(BICPU_FEATURE_CSSC \fP ARM: Common Short Sequence Compression instructions .TP \f(BICPU_FEATURE_DEBUGV8P9 \fP ARM: Debug v8\&.9 .TP \f(BICPU_FEATURE_DOUBLEFAULT2 \fP ARM: Double Fault Extension v2 .TP \f(BICPU_FEATURE_ECBHB \fP ARM: Exploitative control using branch history information .TP \f(BICPU_FEATURE_FGT2 \fP ARM: Fine-grained traps 2 .TP \f(BICPU_FEATURE_HAFT \fP ARM: Hardware managed Access Flag for Table descriptors .TP \f(BICPU_FEATURE_LRCPC3 \fP ARM: Load-Acquire RCpc instructions version 3 .TP \f(BICPU_FEATURE_MTE4 \fP ARM: Enhanced Memory Tagging Extension .TP \f(BICPU_FEATURE_MTE_ASYNC \fP ARM: Asynchronous reporting of Tag Check Fault .TP \f(BICPU_FEATURE_MTE_CANONICAL_TAGS \fP ARM: Canonical Tag checking for Untagged memory .TP \f(BICPU_FEATURE_MTE_NO_ADDRESS_TAGS \fP ARM: Memory tagging with Address tagging disabled .TP \f(BICPU_FEATURE_MTE_PERM \fP ARM: Allocation tag access permission .TP \f(BICPU_FEATURE_MTE_STORE_ONLY \fP ARM: Store-only Tag Checking .TP \f(BICPU_FEATURE_MTE_TAGGED_FAR \fP ARM: FAR_ELx on a Tag Check Fault .TP \f(BICPU_FEATURE_PFAR \fP ARM: Physical Fault Address Register Extension .TP \f(BICPU_FEATURE_PMUV3_ICNTR \fP ARM: Fixed-function instruction counter .TP \f(BICPU_FEATURE_PMUV3_SS \fP ARM: PMU Snapshot extension .TP \f(BICPU_FEATURE_PMUV3P9 \fP ARM: Armv8\&.9 PMU extensions .TP \f(BICPU_FEATURE_PRFMSLC \fP ARM: SLC target support for PRFM instructions .TP \f(BICPU_FEATURE_RASV2 \fP ARM: RAS Extension v2 .TP \f(BICPU_FEATURE_RPRFM \fP ARM: Support for Range Prefetch Memory instruction .TP \f(BICPU_FEATURE_S1PIE \fP ARM: Stage 1 permission indirections .TP \f(BICPU_FEATURE_S1POE \fP ARM: Stage 1 permission overlays .TP \f(BICPU_FEATURE_S2PIE \fP ARM: Stage 2 permission indirections .TP \f(BICPU_FEATURE_S2POE \fP ARM: Stage 2 permission overlays .TP \f(BICPU_FEATURE_SPECRES2 \fP ARM: Enhanced speculation restriction instructions .TP \f(BICPU_FEATURE_SPE_DPFZS \fP ARM: Disable Cycle Counter on SPE Freeze .TP \f(BICPU_FEATURE_SPEV1P4 \fP ARM: Statistical Profiling Extension version 1\&.4 .TP \f(BICPU_FEATURE_SPMU \fP ARM: System Performance Monitors Extension .TP \f(BICPU_FEATURE_THE \fP ARM: Translation Hardening Extension .TP \f(BICPU_FEATURE_SVE2 \fP ARM: Scalable Vector Extension version 2 .TP \f(BICPU_FEATURE_SVE_AES \fP ARM: Scalable Vector AES instructions .TP \f(BICPU_FEATURE_SVE_BITPERM \fP ARM: Scalable Vector Bit Permutes instructions .TP \f(BICPU_FEATURE_SVE_PMULL128 \fP ARM: SVE single-vector Advanced Encryption Standard and 128-bit polynomial multiply long instructions .TP \f(BICPU_FEATURE_SVE_SHA3 \fP ARM: Scalable Vector SHA3 instructions .TP \f(BICPU_FEATURE_SVE_SM4 \fP ARM: Scalable Vector SM4 instructions .TP \f(BICPU_FEATURE_TME \fP ARM: Transactional Memory Extension .TP \f(BICPU_FEATURE_TRBE \fP ARM: Trace Buffer Extension .TP \f(BICPU_FEATURE_BRBE \fP ARM: Branch Record Buffer Extension .TP \f(BICPU_FEATURE_RME \fP ARM: Realm Management Extension .TP \f(BICPU_FEATURE_SME \fP ARM: Scalable Matrix Extension .TP \f(BICPU_FEATURE_SME_F64F64 \fP ARM: Double-precision floating-point outer product instructions .TP \f(BICPU_FEATURE_SME_FA64 \fP ARM: Full A64 instruction set support in Streaming SVE mode .TP \f(BICPU_FEATURE_SME_I16I64 \fP ARM: 16-bit to 64-bit integer widening outer product instructions .TP \f(BICPU_FEATURE_BRBEV1P1 \fP ARM: Branch Record Buffer Extension version 1\&.1 .TP \f(BICPU_FEATURE_MEC \fP ARM: Memory Encryption Contexts .TP \f(BICPU_FEATURE_SME2 \fP ARM: Scalable Matrix Extensions version 2 .TP \f(BICPU_FEATURE_ABLE \fP ARM: Address Breakpoint Linking Extension .TP \f(BICPU_FEATURE_BWE \fP ARM: Breakpoint and watchpoint enhancements .TP \f(BICPU_FEATURE_D128 \fP ARM: 128-bit Translation Tables, 56 bit PA .TP \f(BICPU_FEATURE_EBEP \fP ARM: Exception-based Event Profiling .TP \f(BICPU_FEATURE_GCS \fP ARM: Guarded Control Stack Extension .TP \f(BICPU_FEATURE_ITE \fP ARM: Instrumentation Trace Extension .TP \f(BICPU_FEATURE_LSE128 \fP ARM: 128-bit Atomics .TP \f(BICPU_FEATURE_LVA3 \fP ARM: 56-bit VA .TP \f(BICPU_FEATURE_SEBEP \fP ARM: Synchronous Exception-based Event Profiling .TP \f(BICPU_FEATURE_SME2P1 \fP ARM: Scalable Matrix Extension version 2\&.1 .TP \f(BICPU_FEATURE_SME_F16F16 \fP ARM: Non-widening half-precision FP16 to FP16 arithmetic for SME2 .TP \f(BICPU_FEATURE_SVE2P1 \fP ARM: Scalable Vector Extensions version 2\&.1 .TP \f(BICPU_FEATURE_SVE_B16B16 \fP ARM: Non-widening BFloat16 to BFloat16 arithmetic for SVE2 and SME2 .TP \f(BICPU_FEATURE_SYSINSTR128 \fP ARM: 128-bit System instructions .TP \f(BICPU_FEATURE_SYSREG128 \fP ARM: 128-bit System registers .TP \f(BICPU_FEATURE_TRBE_EXT \fP ARM: Trace Buffer external mode .TP \f(BICPU_FEATURE_ASID2 \fP ARM: Support for concurrent use of two ASIDs .TP \f(BICPU_FEATURE_BWE2 \fP ARM: Breakpoint and watchpoint enhancements 2 .TP \f(BICPU_FEATURE_CPA \fP ARM: Instruction-only Checked Pointer Arithmetic .TP \f(BICPU_FEATURE_CPA2 \fP ARM: Checked Pointer Arithmetic .TP \f(BICPU_FEATURE_E2H0 \fP ARM: Programming of HCR_EL2\&.E2H\&. .TP \f(BICPU_FEATURE_E3DSE \fP ARM: Delegated SError exception injection .TP \f(BICPU_FEATURE_ETS3 \fP ARM: Enhanced Translation Synchronization .TP \f(BICPU_FEATURE_FAMINMAX \fP ARM: Floating-point maximum and minimum absolute value instructions .TP \f(BICPU_FEATURE_FGWTE3 \fP ARM: Fine-Grained Write Trap EL3 .TP \f(BICPU_FEATURE_FP8 \fP ARM: FP8 convert instructions .TP \f(BICPU_FEATURE_FP8DOT2 \fP ARM: FP8 2-way dot product to half-precision instructions .TP \f(BICPU_FEATURE_FP8DOT4 \fP ARM: FP8 4-way dot product to single-precision instructions .TP \f(BICPU_FEATURE_FP8FMA \fP ARM: FP8 multiply-accumulate to half-precision and single-precision instructions .TP \f(BICPU_FEATURE_FPMR \fP ARM: Floating-point Mode Register .TP \f(BICPU_FEATURE_HACDBS \fP ARM: Hardware accelerator for cleaning Dirty state .TP \f(BICPU_FEATURE_HDBSS \fP ARM: Hardware Dirty state tracking structure .TP \f(BICPU_FEATURE_LUT \fP ARM: Lookup table instructions with 2-bit and 4-bit indices .TP \f(BICPU_FEATURE_PAUTH_LR \fP ARM: Pointer authentication instructions that allow signing of LR using SP and PC as diversifiers .TP \f(BICPU_FEATURE_RME_GPC2 \fP ARM: RME Granule Protection Check 2 Extension .TP \f(BICPU_FEATURE_SME_F8F16 \fP ARM: SME2 ZA-targeting FP8 multiply-accumulate, dot product, and outer product to half-precision instructions .TP \f(BICPU_FEATURE_SME_F8F32 \fP ARM: SME2 ZA-targeting FP8 multiply-accumulate, dot product, and outer product to single-precision instructions .TP \f(BICPU_FEATURE_SME_LUTV2 \fP ARM: Lookup table instructions with 4-bit indices and 8-bit elements .TP \f(BICPU_FEATURE_SPMU2 \fP ARM: System Performance Monitors Extension version 2 .TP \f(BICPU_FEATURE_SSVE_FP8DOT2 \fP ARM: SVE FP8 2-way dot product to half-precision instructions in Streaming SVE mode .TP \f(BICPU_FEATURE_SSVE_FP8DOT4 \fP ARM: SVE2 FP8 4-way dot product to single-precision instructions in Streaming SVE mode .TP \f(BICPU_FEATURE_SSVE_FP8FMA \fP ARM: SVE2 FP8 multiply-accumulate to half-precision and single-precision instructions in Streaming SVE mode .TP \f(BICPU_FEATURE_STEP2 \fP ARM: Enhanced Software Step Extension .TP \f(BICPU_FEATURE_TLBIW \fP ARM: TLBI VMALL for Dirty state .SS "enum \fBcpu_hint_t\fP" .PP CPU detection hints identifiers\&. Usage: similar to the flags usage .PP \fBEnumerator\fP .in +1c .TP \f(BICPU_HINT_SSE_SIZE_AUTH \fP SSE unit size is authoritative (not only a Family/Model guesswork, but based on an actual CPUID bit) .SS "enum \fBcpu_msrinfo_request_t\fP" .PP \fBEnumerator\fP .in +1c .TP \f(BIINFO_MPERF \fP Maximum performance frequency clock\&. This is a counter, which increments as a proportion of the actual processor speed\&. .TP \f(BIINFO_APERF \fP Actual performance frequency clock\&. This accumulates the core clock counts when the core is active\&. .TP \f(BIINFO_MIN_MULTIPLIER \fP Minimum CPU:FSB ratio for this CPU, multiplied by 100\&. .TP \f(BIINFO_CUR_MULTIPLIER \fP Current CPU:FSB ratio, multiplied by 100\&. e\&.g\&., a CPU:FSB value of 18\&.5 reads as "1850"\&. .TP \f(BIINFO_MAX_MULTIPLIER \fP Maximum CPU:FSB ratio for this CPU, multiplied by 100\&. .TP \f(BIINFO_TEMPERATURE \fP The current core temperature in Celsius\&. .TP \f(BIINFO_THROTTLING \fP 1 if the current logical processor is throttling\&. 0 if it is running normally\&. .TP \f(BIINFO_VOLTAGE \fP The current core voltage in Volt, multiplied by 100\&. .TP \f(BIINFO_BCLK \fP See \fBINFO_BUS_CLOCK\fP\&. .TP \f(BIINFO_BUS_CLOCK \fP The main bus clock in MHz, e\&.g\&., FSB/QPI/DMI/HT base clock, multiplied by 100\&. .SS "enum \fBcpu_purpose_t\fP" .PP CPU purpose\&. .PP \fBEnumerator\fP .in +1c .TP \f(BIPURPOSE_GENERAL \fP general purpose CPU .TP \f(BIPURPOSE_PERFORMANCE \fP performance CPU .TP \f(BIPURPOSE_EFFICIENCY \fP efficiency CPU .TP \f(BIPURPOSE_LP_EFFICIENCY \fP low-power efficiency CPU .TP \f(BIPURPOSE_U_PERFORMANCE \fP ultimate performance CPU .TP \f(BINUM_CPU_PURPOSES \fP Valid CPU purpose ids: 0\&.\&.NUM_CPU_PURPOSES - 1 .SS "enum \fBcpu_sgx_feature_t\fP" .PP SGX features flags\&. .PP \fBSee also\fP .RS 4 \fBcpu_sgx_t\fP .RE .PP Usage: .PP .nf \&.\&.\&. struct cpu_raw_data_t raw; struct cpu_id_t id; if (cpuid_get_raw_data(&raw) == 0 && cpu_identify(&raw, &id) == 0 && id\&.sgx\&.present) { if (id\&.sgx\&.flags[INTEL_SGX1]) // The CPU has SGX1 instructions support\&.\&.\&. \&.\&.\&. } else { // no SGX } } else { // processor cannot be determined\&. } .fi .PP .PP \fBEnumerator\fP .in +1c .TP \f(BIINTEL_SGX1 \fP SGX1 instructions support .TP \f(BIINTEL_SGX2 \fP SGX2 instructions support .SS "enum \fBcpu_vendor_t\fP" .PP CPU vendor, as guessed from the Vendor String\&. .PP \fBEnumerator\fP .in +1c .TP \f(BIVENDOR_INTEL \fP Intel CPU .TP \f(BIVENDOR_AMD \fP AMD CPU .TP \f(BIVENDOR_CYRIX \fP Cyrix CPU .TP \f(BIVENDOR_NEXGEN \fP NexGen CPU .TP \f(BIVENDOR_TRANSMETA \fP Transmeta CPU .TP \f(BIVENDOR_UMC \fP x86 CPU by UMC .TP \f(BIVENDOR_CENTAUR \fP x86 CPU by IDT .TP \f(BIVENDOR_RISE \fP x86 CPU by Rise Technology .TP \f(BIVENDOR_SIS \fP x86 CPU by SiS .TP \f(BIVENDOR_NSC \fP x86 CPU by National Semiconductor .TP \f(BIVENDOR_HYGON \fP Hygon CPU .TP \f(BIVENDOR_ARM \fP ARM CPU .TP \f(BIVENDOR_BROADCOM \fP Broadcom Corporation CPU .TP \f(BIVENDOR_CAVIUM \fP Cavium Inc\&. CPU .TP \f(BIVENDOR_DEC \fP Digital Equipment Corporation CPU .TP \f(BIVENDOR_FUJITSU \fP Fujitsu Ltd\&. CPU .TP \f(BIVENDOR_HISILICON \fP HiSilicon Technology Co\&., Ltd\&. CPU .TP \f(BIVENDOR_INFINEON \fP Infineon Technologies AG CPU .TP \f(BIVENDOR_FREESCALE \fP Motorola or Freescale Semiconductor Inc\&. CPU .TP \f(BIVENDOR_NVIDIA \fP NVIDIA Corporation CPU .TP \f(BIVENDOR_APM \fP Applied Micro Circuits Corporation CPU .TP \f(BIVENDOR_QUALCOMM \fP Qualcomm Inc\&. CPU .TP \f(BIVENDOR_SAMSUNG \fP Samsung Group CPU .TP \f(BIVENDOR_MARVELL \fP Marvell International Ltd\&. CPU .TP \f(BIVENDOR_APPLE \fP Apple Inc\&. CPU .TP \f(BIVENDOR_FARADAY \fP Faraday Technology CPU .TP \f(BIVENDOR_MICROSOFT \fP Microsoft Corporation CPU .TP \f(BIVENDOR_PHYTIUM \fP Phytium Technology Co\&., Ltd CPU .TP \f(BIVENDOR_AMPERE \fP Ampere Computing CPU .TP \f(BINUM_CPU_VENDORS \fP Valid CPU vendor ids: 0\&.\&.NUM_CPU_VENDORS - 1 .SS "enum \fBhypervisor_vendor_t\fP" .PP Hypervisor vendor, as guessed from the CPU_FEATURE_HYPERVISOR flag\&. .PP \fBEnumerator\fP .in +1c .TP \f(BIHYPERVISOR_NONE \fP no hypervisor .TP \f(BIHYPERVISOR_BHYVE \fP FreeBSD bhyve hypervisor .TP \f(BIHYPERVISOR_HYPERV \fP Microsoft Hyper-V or Windows Virtual PC hypervisor .TP \f(BIHYPERVISOR_KVM \fP KVM hypervisor .TP \f(BIHYPERVISOR_PARALLELS \fP Parallels hypervisor .TP \f(BIHYPERVISOR_QEMU \fP QEMU hypervisor .TP \f(BIHYPERVISOR_VIRTUALBOX \fP VirtualBox hypervisor .TP \f(BIHYPERVISOR_VMWARE \fP VMware hypervisor .TP \f(BIHYPERVISOR_XEN \fP Xen hypervisor .TP \f(BINUM_HYPERVISOR_VENDORS \fP Valid hypervisor vendor ids: 0\&.\&.NUM_HYPERVISOR_VENDORS - 1 .SH "Function Documentation" .PP .SS "char * affinity_mask_str (\fBcpu_affinity_mask_t\fP * affinity_mask)" .PP Returns textual representation of a CPU affinity mask\&. .PP \fBParameters\fP .RS 4 \fIaffinity_mask\fP - the affinity mask (in hexadecimal), whose textual representation is wanted\&. .RE .PP \fBNote\fP .RS 4 This function is not thread-safe .RE .PP \fBReturns\fP .RS 4 a string like "0000FFFF", "00FF0000", etc\&. .RE .PP .SS "char * affinity_mask_str_r (\fBcpu_affinity_mask_t\fP * affinity_mask, char * buffer, uint32_t buffer_len)" .PP Returns textual representation of a CPU affinity mask (thread-safe) .PP \fBParameters\fP .RS 4 \fIaffinity_mask\fP - Input - the affinity mask (in hexadecimal), whose textual representation is wanted\&. .br \fIbuffer\fP - Output - an allocated string where to store the textual representation, like "0000FFFF", "00FF0000", etc\&. .br \fIbuffer_len\fP - Input - the size of buffer\&. .RE .PP \fBReturns\fP .RS 4 a pointer on buffer .RE .PP .SS "const char * cpu_architecture_str (\fBcpu_architecture_t\fP architecture)" .PP Returns the short textual representation of a CPU architecture\&. .PP \fBParameters\fP .RS 4 \fIarchitecture\fP - the architecture, whose textual representation is wanted\&. .RE .PP \fBReturns\fP .RS 4 a constant string like "x86", "ARM", etc\&. .RE .PP .SS "int cpu_clock (void )" .PP Get the CPU clock frequency (all-in-one method) This is an all-in-one method for getting the CPU clock frequency\&. It tries to use the OS for that\&. If the OS doesn't have this info, it uses cpu_clock_measure with 200ms time interval and quadruple checking\&. .PP \fBReturns\fP .RS 4 the CPU clock frequency in MHz\&. If every possible method fails, the result is -1\&. .RE .PP .SS "int cpu_clock_by_ic (int millis, int runs)" .PP Measure the CPU clock frequency using instruction-counting\&. .PP \fBParameters\fP .RS 4 \fImillis\fP - how much time to allocate for each run, in milliseconds .br \fIruns\fP - how many runs to perform .RE .PP The function performs a busy-wait cycle using a known number of "heavy" (SSE) instructions\&. These instructions run at (more or less guaranteed) 1 IPC rate, so by running a busy loop for a fixed amount of time, and measuring the amount of instructions done, the CPU clock is accurately measured\&. .PP Of course, this function is still affected by the power-saving schemes, so the warnings as of \fBcpu_clock_measure()\fP still apply\&. However, this function is immune to problems with detection, related to the Intel Nehalem's "Turbo" mode, where the internal clock is raised, but the RDTSC rate is unaffected\&. .PP The function will run for about (millis * runs) milliseconds\&. You can make only a single busy-wait run (runs == 1); however, this can be affected by task scheduling (which will break the counting), so allowing more than one run is recommended\&. As run length is not imperative for accurate readings (e\&.g\&., 50ms is sufficient), you can afford a lot of short runs, e\&.g\&. 10 runs of 50ms or 20 runs of 25ms\&. .PP Recommended values - millis = 50, runs = 4\&. For more robustness, increase the number of runs\&. .PP NOTE: on Bulldozer and later CPUs, the busy-wait cycle runs at 1\&.4 IPC, thus the results are skewed\&. This is corrected internally by dividing the resulting value by 1\&.4\&. However, this only occurs if the thread is executed on a single CMT module - if there are other threads competing for resources, the results are unpredictable\&. Make sure you run \fBcpu_clock_by_ic()\fP on a CPU that is free from competing threads, or if there are such threads, they shouldn't exceed the number of modules\&. On a Bulldozer X8, that means 4 threads\&. .PP \fBReturns\fP .RS 4 the CPU clock frequency in MHz (within some measurement error margin)\&. If SSE is not supported, the result is -1\&. If the input parameters are incorrect, or some other internal fault is detected, the result is -2\&. .RE .PP .SS "int cpu_clock_by_mark (struct \fBcpu_mark_t\fP * mark)" .PP Calculates the CPU clock\&. .PP \fBParameters\fP .RS 4 \fImark\fP - pointer to a \fBcpu_mark_t\fP structure, which has been initialized with cpu_tsc_mark and later `stopped' with cpu_tsc_unmark\&. .RE .PP \fBNote\fP .RS 4 For reliable results, the marked time interval should be at least about 10 ms\&. .RE .PP \fBReturns\fP .RS 4 the CPU clock frequency, in MHz\&. Due to measurement error, it will differ from the true value in a few least-significant bits\&. Accuracy depends on the timing interval - the more, the better\&. If the timing interval is insufficient, the result is -1\&. Also, see the comment on cpu_clock_measure for additional issues and pitfalls in using RDTSC for CPU frequency measurements\&. .RE .PP .SS "int cpu_clock_by_os (void )" .PP Returns the CPU clock, as reported by the OS\&. This function uses OS-specific functions to obtain the CPU clock\&. It may differ from the true clock for several reasons: .br .br .PP i) The CPU might be in some power saving state, while the OS reports its full-power frequency, or vice-versa\&. .br ii) In some cases you can raise or lower the CPU frequency with overclocking utilities and the OS will not notice\&. .PP \fBReturns\fP .RS 4 the CPU clock frequency in MHz\&. If the OS is not (yet) supported or lacks the necessary reporting machinery, the return value is -1 .RE .PP .SS "int cpu_clock_by_tsc (struct \fBcpu_raw_data_t\fP * raw)" .PP Measure the CPU clock frequency using TSC frequency from CPUID\&. .PP \fBParameters\fP .RS 4 \fIraw\fP - Optional input - a pointer to the raw CPUID data, which is obtained either by cpuid_get_raw_data or cpuid_deserialize_raw_data\&. Can also be NULL, in which case the functions calls cpuid_get_raw_data itself\&. .RE .PP The function read Time Stamp Counter and Nominal Core Crystal Clock Information Leaf from CPUID\&. It determines the processor base frequency\&. .PP NOTE: only x86 Intel CPUs since Skylake (6th generation of Intel Core processors) are supported\&. Other vendors do not support this feature\&. .PP \fBReturns\fP .RS 4 the CPU clock frequency in MHz\&. If TSC frequency is not supported, the result is -1\&. If the input parameters are incorrect, or some other internal fault is detected, the result is -2\&. .RE .PP .SS "int cpu_clock_measure (int millis, int quad_check)" .PP Measure the CPU clock frequency\&. .PP \fBParameters\fP .RS 4 \fImillis\fP - How much time to waste in the busy-wait cycle\&. In millisecs\&. Useful values 10 - 1000 .br \fIquad_check\fP - Do a more thorough measurement if nonzero (see the explanation)\&. .RE .PP The function performs a busy-wait cycle for the given time and calculates the CPU frequency by the difference of the TSC values\&. The accuracy of the calculation depends on the length of the busy-wait cycle: more is better, but 100ms should be enough for most purposes\&. .PP While this will calculate the CPU frequency correctly in most cases, there are several reasons why it might be incorrect: .br .PP i) RDTSC doesn't guarantee it will run at the same clock as the CPU\&. Apparently there aren't CPUs at the moment, but still, there's no guarantee\&. .br ii) The CPU might be in a low-frequency power saving mode, and the CPU might be switched to higher frequency at any time\&. If this happens during the measurement, the result can be anywhere between the low and high frequencies\&. Also, if you're interested in the high frequency value only, this function might return the low one instead\&. .br iii) On SMP systems exhibiting TSC drift (see \fBcpu_rdtsc\fP) .PP the quad_check option will run four consecutive measurements and then return the average of the two most-consistent results\&. The total runtime of the function will still be `millis' - consider using a bit more time for the timing interval\&. .PP Finally, for benchmarking / CPU intensive applications, the best strategy is to use the \fBcpu_tsc_mark()\fP / \fBcpu_tsc_unmark()\fP / \fBcpu_clock_by_mark()\fP method\&. Begin by mark()-ing about one second after application startup (allowing the power-saving manager to kick in and rise the frequency during that time), then unmark() just before application finishing\&. The result will most acurately represent at what frequency your app was running\&. .PP \fBReturns\fP .RS 4 the CPU clock frequency in MHz (within some measurement error margin)\&. If RDTSC is not supported, the result is -1\&. .RE .PP .SS "void cpu_exec_cpuid (uint32_t eax, uint32_t * regs)" .PP Executes the CPUID instruction\&. .PP \fBParameters\fP .RS 4 \fIeax\fP - the value of the EAX register when executing CPUID .br \fIregs\fP - the results will be stored here\&. regs[0] = EAX, regs[1] = EBX, \&.\&.\&. .RE .PP \fBNote\fP .RS 4 CPUID will be executed with EAX set to the given value and EBX, ECX, EDX set to zero\&. .RE .PP .SS "void cpu_exec_cpuid_ext (uint32_t * regs)" .PP Executes the CPUID instruction with the given input registers\&. .PP \fBNote\fP .RS 4 This is just a bit more generic version of cpu_exec_cpuid - it allows you to control all the registers\&. .RE .PP \fBParameters\fP .RS 4 \fIregs\fP - Input/output\&. Prior to executing CPUID, EAX, EBX, ECX and EDX will be set to regs[0], regs[1], regs[2] and regs[3]\&. After CPUID, this array will contain the results\&. .RE .PP .SS "const char * cpu_feature_level_str (\fBcpu_feature_level_t\fP level)" .PP Returns the short textual representation of a CPU feature level\&. .PP \fBParameters\fP .RS 4 \fIlevel\fP - the feature level, whose textual representation is wanted\&. .RE .PP \fBReturns\fP .RS 4 a constant string like "ARMv8\&.0-A", "ARMv9\&.4-A", etc\&. .RE .PP .SS "const char * cpu_feature_str (\fBcpu_feature_t\fP feature)" .PP Returns the short textual representation of a CPU flag\&. .PP \fBParameters\fP .RS 4 \fIfeature\fP - the feature, whose textual representation is wanted\&. .RE .PP \fBReturns\fP .RS 4 a constant string like "fpu", "tsc", "sse2", etc\&. .RE .PP \fBNote\fP .RS 4 the names of the returned flags are compatible with those from /proc/cpuinfo in Linux, with the exception of `tm_amd' .RE .PP .SS "int cpu_identify (struct \fBcpu_raw_data_t\fP * raw, struct \fBcpu_id_t\fP * data)" .PP Identifies the CPU\&. .PP \fBParameters\fP .RS 4 \fIraw\fP - Input - a pointer to the raw CPUID data, which is obtained either by cpuid_get_raw_data or cpuid_deserialize_raw_data\&. Can also be NULL, in which case the functions calls cpuid_get_raw_data itself\&. .br \fIdata\fP - Output - the decoded CPU features/info is written here\&. .RE .PP \fBNote\fP .RS 4 The function will not fail, even if some of the information cannot be obtained\&. Even when the CPU is new and thus unknown to libcpuid, some generic info, such as "AMD K9 family CPU" will be written to data\&.cpu_codename, and most other things, such as the CPU flags, cache sizes, etc\&. should be detected correctly anyway\&. However, the function CAN fail, if the CPU is completely alien to libcpuid\&. .PP While \fBcpu_identify()\fP and \fBcpuid_get_raw_data()\fP are fast for most purposes, running them several thousand times per second can hamper performance significantly\&. Specifically, avoid writing "cpu feature checker" wrapping function, which calls cpu_identify and returns the value of some flag, if that function is going to be called frequently\&. .RE .PP \fBReturns\fP .RS 4 zero if successful, and some negative number on error\&. The error message can be obtained by calling \fBcpuid_error\fP\&. .RE .PP \fBSee also\fP .RS 4 \fBcpu_error_t\fP .RE .PP .SS "int cpu_identify_all (struct \fBcpu_raw_data_array_t\fP * raw_array, struct \fBsystem_id_t\fP * system)" .PP Identifies all the CPUs\&. .PP \fBParameters\fP .RS 4 \fIraw_array\fP - Input - a pointer to the array of raw CPUID data, which is obtained either by cpuid_get_all_raw_data or cpuid_deserialize_all_raw_data\&. Can also be NULL, in which case the functions calls cpuid_get_all_raw_data itself\&. .br \fIsystem\fP - Output - the decoded CPU features/info is written here for each CPU type\&. .RE .PP \fBNote\fP .RS 4 The function is similar to cpu_identify\&. Refer to cpu_identify notes\&. .PP As the memory is dynamically allocated, be sure to call \fBcpuid_free_raw_data_array()\fP and \fBcpuid_free_system_id()\fP after you're done with the data .RE .PP \fBReturns\fP .RS 4 zero if successful, and some negative number on error\&. The error message can be obtained by calling \fBcpuid_error\fP\&. .RE .PP \fBSee also\fP .RS 4 \fBcpu_error_t\fP .RE .PP .SS "int cpu_msr_driver_close (struct msr_driver_t * handle)" .PP Closes an open MSR driver\&. This function unloads the MSR driver opened by cpu_msr_driver_open and frees any resources associated with it\&. .PP \fBParameters\fP .RS 4 \fIhandle\fP - a handle to the MSR reader driver, as created by cpu_msr_driver_open .RE .PP \fBReturns\fP .RS 4 zero if successful, and some negative number on error\&. The error message can be obtained by calling \fBcpuid_error\fP\&. .RE .PP \fBSee also\fP .RS 4 \fBcpu_error_t\fP .RE .PP .SS "struct msr_driver_t * cpu_msr_driver_open (void )" .PP Starts/opens a driver, needed to read MSRs (Model Specific Registers) On systems that support it, this function will create a temporary system driver, that has privileges to execute the RDMSR instruction\&. After the driver is created, you can read MSRs by calling \fBcpu_rdmsr\fP .PP \fBReturns\fP .RS 4 a handle to the driver on success, and NULL on error\&. The error message can be obtained by calling \fBcpuid_error\fP\&. .RE .PP \fBSee also\fP .RS 4 \fBcpu_error_t\fP .RE .PP .SS "struct msr_driver_t * cpu_msr_driver_open_core (unsigned core_num)" .PP Similar to \fBcpu_msr_driver_open\fP, but accept one parameter\&. This function works on certain operating systems (GNU/Linux, FreeBSD) .PP \fBParameters\fP .RS 4 \fIcore_num\fP specify the core number for MSR\&. The first core number is 0\&. The last core number is \fBcpuid_get_total_cpus\fP - 1\&. .RE .PP \fBReturns\fP .RS 4 a handle to the driver on success, and NULL on error\&. The error message can be obtained by calling \fBcpuid_error\fP\&. .RE .PP \fBSee also\fP .RS 4 \fBcpu_error_t\fP .RE .PP .SS "int cpu_msrinfo (struct msr_driver_t * handle, \fBcpu_msrinfo_request_t\fP which)" .PP Reads extended CPU information from Model-Specific Registers\&. .PP \fBParameters\fP .RS 4 \fIhandle\fP - a handle to an open MSR driver, .RE .PP \fBSee also\fP .RS 4 \fBcpu_msr_driver_open\fP .RE .PP \fBParameters\fP .RS 4 \fIwhich\fP - which info field should be returned\&. A list of available information entities is listed in the \fBcpu_msrinfo_request_t\fP enum\&. .RE .PP \fBReturn values\fP .RS 4 \fI-\fP if the requested information is available for the current processor model, the respective value is returned\&. if no information is available, or the CPU doesn't support the query, the special value CPU_INVALID_VALUE is returned .RE .PP \fBNote\fP .RS 4 This function is not MT-safe\&. If you intend to call it from multiple threads, guard it through a mutex or a similar primitive\&. .RE .PP .SS "const char * cpu_purpose_str (\fBcpu_purpose_t\fP purpose)" .PP Returns the short textual representation of a CPU purpose\&. .PP \fBParameters\fP .RS 4 \fIpurpose\fP - the purpose, whose textual representation is wanted\&. .RE .PP \fBReturns\fP .RS 4 a constant string like "general", "performance", "efficiency", etc\&. .RE .PP .SS "int cpu_rdmsr (struct msr_driver_t * handle, uint32_t msr_index, uint64_t * result)" .PP Reads a Model-Specific Register (MSR) If the CPU has MSRs (as indicated by the CPU_FEATURE_MSR flag), you can read a MSR with the given index by calling this function\&. .PP There are several prerequisites you must do before reading MSRs: 1) You must ensure the CPU has RDMSR\&. Check the CPU_FEATURE_MSR flag in \fBcpu_id_t::flags\fP 2) You must ensure that the CPU implements the specific MSR you intend to read\&. 3) You must open a MSR-reader driver\&. RDMSR is a privileged instruction and needs ring-0 access in order to work\&. This temporary driver is created by calling \fBcpu_msr_driver_open\fP .PP \fBParameters\fP .RS 4 \fIhandle\fP - a handle to the MSR reader driver, as created by cpu_msr_driver_open .br \fImsr_index\fP - the numeric ID of the MSR you want to read .br \fIresult\fP - a pointer to a 64-bit integer, where the MSR value is stored .RE .PP \fBReturns\fP .RS 4 zero if successful, and some negative number on error\&. The error message can be obtained by calling \fBcpuid_error\fP\&. .RE .PP \fBSee also\fP .RS 4 \fBcpu_error_t\fP .RE .PP .SS "int cpu_rdmsr_range (struct msr_driver_t * handle, uint32_t msr_index, uint8_t highbit, uint8_t lowbit, uint64_t * result)" .PP Similar to \fBcpu_rdmsr\fP, but extract a range of bits\&. .PP \fBParameters\fP .RS 4 \fIhandle\fP - a handle to the MSR reader driver, as created by cpu_msr_driver_open .br \fImsr_index\fP - the numeric ID of the MSR you want to read .br \fIhighbit\fP - the high bit in range, must be inferior to 64 .br \fIlowbit\fP - the low bit in range, must be equal or superior to 0 .br \fIresult\fP - a pointer to a 64-bit integer, where the MSR value is stored .RE .PP \fBReturns\fP .RS 4 zero if successful, and some negative number on error\&. The error message can be obtained by calling \fBcpuid_error\fP\&. .RE .PP \fBSee also\fP .RS 4 \fBcpu_error_t\fP .RE .PP .SS "void cpu_rdtsc (uint64_t * result)" .PP Executes RDTSC\&. The RDTSC (ReaD Time Stamp Counter) instruction gives access to an internal 64-bit counter, which usually increments at each clock cycle\&. This can be used for various timing routines, and as a very precise clock source\&. It is set to zero on system startup\&. Beware that may not increment at the same frequency as the CPU\&. Consecutive calls of RDTSC are, however, guaranteed to return monotonically-increasing values\&. .PP \fBParameters\fP .RS 4 \fIresult\fP - a pointer to a 64-bit unsigned integer, where the TSC value will be stored .RE .PP \fBNote\fP .RS 4 If 100% compatibility is a concern, you must first check if the RDTSC instruction is present (if it is not, your program will crash with "invalid opcode" exception)\&. Only some very old processors (i486, early AMD K5 and some Cyrix CPUs) lack that instruction - they should have become exceedingly rare these days\&. To verify RDTSC presence, run \fBcpu_identify()\fP and check flags[CPU_FEATURE_TSC]\&. .PP The monotonically increasing nature of the TSC may be violated on SMP systems, if their TSC clocks run at different rate\&. If the OS doesn't account for that, the TSC drift may become arbitrary large\&. .RE .PP .SS "int cpu_request_core_type (\fBcpu_purpose_t\fP purpose, struct \fBcpu_raw_data_array_t\fP * raw_array, struct \fBcpu_id_t\fP * data)" .PP Identifies a given CPU type\&. .PP \fBParameters\fP .RS 4 \fIpurpose\fP - Input - a \fBcpu_purpose_t\fP to request .br \fIraw_array\fP - Optional input - a pointer to the array of raw CPUID data, which is obtained either by cpuid_get_all_raw_data or cpuid_deserialize_all_raw_data\&. Can also be NULL, in which case the functions calls cpuid_get_all_raw_data itself\&. .br \fIdata\fP - Output - the decoded CPU features/info is written here\&. .RE .PP \fBReturns\fP .RS 4 zero if successful, and some negative number on error (like ERR_NOT_FOUND if CPU type not found)\&. The error message can be obtained by calling \fBcpuid_error\fP\&. .RE .PP \fBSee also\fP .RS 4 \fBcpu_error_t\fP .RE .PP .SS "void cpu_tsc_mark (struct \fBcpu_mark_t\fP * mark)" .PP Store TSC and timing info\&. This function stores the current TSC value and current time info from a precise OS-specific clock source in the \fBcpu_mark_t\fP structure\&. The sys_clock field contains time with microsecond resolution\&. The values can later be used to measure time intervals, number of clocks, FPU frequency, etc\&. .PP \fBSee also\fP .RS 4 \fBcpu_rdtsc\fP .RE .PP \fBParameters\fP .RS 4 \fImark\fP [out] - a pointer to a \fBcpu_mark_t\fP structure .RE .PP .SS "void cpu_tsc_unmark (struct \fBcpu_mark_t\fP * mark)" .PP Calculate TSC and timing difference\&. .PP \fBParameters\fP .RS 4 \fImark\fP - input/output: a pointer to a \fBcpu_mark_t\fP structure, which has already been initialized by cpu_tsc_mark\&. The difference in TSC and time will be written here\&. .RE .PP This function calculates the TSC and time difference, by obtaining the current TSC and timing values and subtracting the contents of the `mark' structure from them\&. Results are written in the same structure\&. .PP Example: .PP .nf \&.\&.\&. struct cpu_mark_t mark; cpu_tsc_mark(&mark); foo(); cpu_tsc_unmark(&mark); printf("Foo finished\&. Executed in %llu cycles and %llu usecs\\n", mark\&.tsc, mark\&.sys_clock); \&.\&.\&. .fi .PP .SS "int cpuid_deserialize_all_raw_data (struct \fBcpu_raw_data_array_t\fP * data, const char * filename)" .PP Reads all raw CPUID data from file\&. .PP \fBParameters\fP .RS 4 \fIdata\fP - a pointer to \fBcpu_raw_data_array_t\fP structure\&. The deserialized array data will be written here\&. .br \fIfilename\fP - the path of the file, containing the serialized raw data\&. If empty, stdin will be used\&. .RE .PP \fBNote\fP .RS 4 This function may fail, if the file is created by different version of the library\&. Also, see the notes on cpuid_serialize_all_raw_data\&. .PP As the memory is dynamically allocated, be sure to call \fBcpuid_free_raw_data_array()\fP after you're done with the data .RE .PP \fBReturns\fP .RS 4 zero if successful, and some negative number on error\&. The error message can be obtained by calling \fBcpuid_error\fP\&. .RE .PP \fBSee also\fP .RS 4 \fBcpu_error_t\fP .RE .PP .SS "int cpuid_deserialize_raw_data (struct \fBcpu_raw_data_t\fP * data, const char * filename)" .PP Reads raw CPUID data from file\&. .PP \fBParameters\fP .RS 4 \fIdata\fP - a pointer to \fBcpu_raw_data_t\fP structure\&. The deserialized data will be written here\&. .br \fIfilename\fP - the path of the file, containing the serialized raw data\&. If empty, stdin will be used\&. .RE .PP \fBNote\fP .RS 4 This function may fail, if the file is created by different version of the library\&. Also, see the notes on cpuid_serialize_raw_data\&. .RE .PP \fBReturns\fP .RS 4 zero if successful, and some negative number on error\&. The error message can be obtained by calling \fBcpuid_error\fP\&. .RE .PP \fBSee also\fP .RS 4 \fBcpu_error_t\fP .RE .PP .SS "const char * cpuid_error (void )" .PP Returns textual description of the last error\&. libcpuid stores an `errno'-style error status, whose description can be obtained with this function\&. .PP \fBNote\fP .RS 4 This function is not thread-safe .RE .PP \fBSee also\fP .RS 4 \fBcpu_error_t\fP .RE .PP .SS "void cpuid_free_cpu_list (struct \fBcpu_list_t\fP * list)" .PP Frees a CPU list\&. This function deletes all the memory associated with a CPU list, as obtained by \fBcpuid_get_cpu_list()\fP .PP \fBParameters\fP .RS 4 \fIlist\fP - the list to be free()'d\&. .RE .PP .SS "void cpuid_free_raw_data_array (struct \fBcpu_raw_data_array_t\fP * raw_array)" .PP Frees a raw array\&. This function deletes all the memory associated with a raw array, as obtained by \fBcpuid_get_all_raw_data()\fP, \fBcpuid_deserialize_all_raw_data()\fP and \fBcpu_identify_all()\fP .PP \fBParameters\fP .RS 4 \fIraw_array\fP - the raw array to be free()'d\&. .RE .PP .SS "void cpuid_free_system_id (struct \fBsystem_id_t\fP * system)" .PP Frees a system ID type\&. This function deletes all the memory associated with a system ID, as obtained by \fBcpu_identify_all()\fP .PP \fBParameters\fP .RS 4 \fIsystem\fP - the system ID to be free()'d\&. .RE .PP .SS "int cpuid_get_all_raw_data (struct \fBcpu_raw_data_array_t\fP * data)" .PP Obtains the raw CPUID data from all CPUs\&. .PP \fBParameters\fP .RS 4 \fIdata\fP - a pointer to \fBcpu_raw_data_array_t\fP structure .RE .PP \fBNote\fP .RS 4 As the memory is dynamically allocated, be sure to call \fBcpuid_free_raw_data_array()\fP after you're done with the data .RE .PP \fBReturns\fP .RS 4 zero if successful, and some negative number on error\&. The error message can be obtained by calling \fBcpuid_error\fP\&. .RE .PP \fBSee also\fP .RS 4 \fBcpu_error_t\fP .RE .PP .SS "void cpuid_get_cpu_list (\fBcpu_vendor_t\fP vendor, struct \fBcpu_list_t\fP * list)" .PP Gets a list of all known CPU names from a specific vendor\&. This function compiles a list of all known CPU (code)names (i\&.e\&. the possible values of \fBcpu_id_t::cpu_codename\fP) for the given vendor\&. .PP There are about 100 entries for Intel and AMD, and a few for the other vendors\&. The list is written out in approximate chronological introduction order of the parts\&. .PP \fBParameters\fP .RS 4 \fIvendor\fP the vendor to be queried .br \fIlist\fP [out] the resulting list will be written here\&. On failure, num_entries is set to zero and names to NULL\&. The error message can be obtained by calling \fBcpuid_error\fP\&. .RE .PP \fBSee also\fP .RS 4 \fBcpu_error_t\fP NOTE: As the memory is dynamically allocated, be sure to call \fBcpuid_free_cpu_list()\fP after you're done with the data .PP \fBcpu_list_t\fP .RE .PP .SS "struct \fBcpu_epc_t\fP cpuid_get_epc (int index, const struct \fBcpu_raw_data_t\fP * raw)" .PP Fetches information about an EPC (Enclave Page Cache) area\&. .PP \fBParameters\fP .RS 4 \fIindex\fP - zero-based index, valid range [0\&.\&.cpu_id_t\&.egx\&.num_epc_sections) .br \fIraw\fP - a pointer to fetched raw CPUID data\&. Needed only for testing, you can safely pass NULL here (if you pass a real structure, it will be used for fetching the leaf 12h data if index < 2; otherwise the real CPUID instruction will be used)\&. .RE .PP \fBReturns\fP .RS 4 the requested data\&. If the CPU doesn't support SGX, or if index >= cpu_id_t\&.egx\&.num_epc_sections, both fields of the returned structure will be zeros\&. .RE .PP .PP References \fBcpuid_get_epc()\fP\&. .PP Referenced by \fBcpuid_get_epc()\fP\&. .SS "\fBhypervisor_vendor_t\fP cpuid_get_hypervisor (struct \fBcpu_raw_data_t\fP * raw, struct \fBcpu_id_t\fP * data)" .PP Obtains the hypervisor vendor from CPUID from the current CPU\&. .PP \fBParameters\fP .RS 4 \fIraw\fP - Optional input - a pointer to the raw CPUID data, which is obtained either by cpuid_get_raw_data or cpuid_deserialize_raw_data\&. Can also be NULL, in which case the functions calls cpuid_get_raw_data itself\&. .br \fIdata\fP - Optional input - the decoded CPU features/info is written here\&. Can also be NULL, in which case the functions calls cpu_identify itself\&. .RE .PP \fBNote\fP .RS 4 If no hypervisor is detected, the hypervisor can be hidden in some cases\&. Refer to https://github.com/anrieff/libcpuid/issues/90#issuecomment-296568713\&. .RE .PP \fBReturns\fP .RS 4 HYPERVISOR_UNKNOWN if failed, HYPERVISOR_NONE if no hypervisor detected (or hidden), otherwise the hypervisor vendor type\&. .RE .PP \fBSee also\fP .RS 4 \fBhypervisor_vendor_t\fP .RE .PP .SS "int cpuid_get_raw_data (struct \fBcpu_raw_data_t\fP * data)" .PP Obtains the raw CPUID data from the current CPU\&. .PP \fBParameters\fP .RS 4 \fIdata\fP - a pointer to \fBcpu_raw_data_t\fP structure .RE .PP \fBReturns\fP .RS 4 zero if successful, and some negative number on error\&. The error message can be obtained by calling \fBcpuid_error\fP\&. .RE .PP \fBSee also\fP .RS 4 \fBcpu_error_t\fP .RE .PP .SS "int cpuid_get_raw_data_core (struct \fBcpu_raw_data_t\fP * data, logical_cpu_t logical_cpu)" .PP Obtains the raw CPUID data from the specified CPU\&. .PP \fBParameters\fP .RS 4 \fIdata\fP - a pointer to \fBcpu_raw_data_t\fP structure .br \fIlogical_cpu\fP specify the core number\&. The first core number is 0\&. The last core number is \fBcpuid_get_total_cpus\fP - 1\&. .RE .PP \fBReturns\fP .RS 4 zero if successful, and some negative number on error\&. The error message can be obtained by calling \fBcpuid_error\fP\&. .RE .PP \fBSee also\fP .RS 4 \fBcpu_error_t\fP .RE .PP .SS "int cpuid_get_total_cpus (void )" .PP Returns the total number of logical CPU threads (even if CPUID is not present)\&. Under VM, this number (and total_logical_cpus, since they are fetched with the same code) may be nonsensical, i\&.e\&. might not equal NumPhysicalCPUs*NumCoresPerCPU*HyperThreading\&. This is because no matter how many logical threads the host machine has, you may limit them in the VM to any number you like\&. \fBThis\fP is the number returned by \fBcpuid_get_total_cpus()\fP\&. .PP \fBReturns\fP .RS 4 Number of logical CPU threads available\&. Equals the \fBcpu_id_t::total_logical_cpus\fP\&. .RE .PP .SS "\fBcpu_vendor_t\fP cpuid_get_vendor (void )" .PP Obtains the CPU vendor from CPUID from the current CPU\&. .PP \fBNote\fP .RS 4 The result is cached\&. .RE .PP \fBReturns\fP .RS 4 VENDOR_UNKNOWN if failed, otherwise the CPU vendor type\&. .RE .PP \fBSee also\fP .RS 4 \fBcpu_vendor_t\fP .RE .PP .SS "const char * cpuid_lib_version (void )" .PP Returns the libcpuid version\&. .PP \fBReturns\fP .RS 4 the string representation of the libcpuid version, like "0\&.1\&.1" .RE .PP .SS "int cpuid_present (void )" .PP Checks if the CPUID instruction is supported\&. .PP \fBReturn values\fP .RS 4 \fI1\fP if CPUID is present .br \fI0\fP the CPU doesn't have CPUID\&. .RE .PP .SS "int cpuid_serialize_all_raw_data (struct \fBcpu_raw_data_array_t\fP * data, const char * filename)" .PP Writes all the raw CPUID data to a text file\&. .PP \fBParameters\fP .RS 4 \fIdata\fP - a pointer to \fBcpu_raw_data_array_t\fP structure .br \fIfilename\fP - the path of the file, where the serialized data for all CPUs should be written\&. If empty, stdout will be used\&. .RE .PP \fBNote\fP .RS 4 This is intended primarily for debugging\&. On some processor, which is not currently supported or not completely recognized by cpu_identify_all, one can still successfully get the raw data and write it to a file\&. libcpuid developers can later import this file and debug the detection code as if running on the actual hardware\&. The file is simple text format of "something=value" pairs\&. Version info is also written, but the format is not intended to be neither backward- nor forward compatible\&. .RE .PP \fBReturns\fP .RS 4 zero if successful, and some negative number on error\&. The error message can be obtained by calling \fBcpuid_error\fP\&. .RE .PP \fBSee also\fP .RS 4 \fBcpu_error_t\fP .RE .PP .SS "int cpuid_serialize_raw_data (struct \fBcpu_raw_data_t\fP * data, const char * filename)" .PP Writes the raw CPUID data to a text file\&. .PP \fBParameters\fP .RS 4 \fIdata\fP - a pointer to \fBcpu_raw_data_t\fP structure .br \fIfilename\fP - the path of the file, where the serialized data should be written\&. If empty, stdout will be used\&. .RE .PP \fBNote\fP .RS 4 This is intended primarily for debugging\&. On some processor, which is not currently supported or not completely recognized by cpu_identify, one can still successfully get the raw data and write it to a file\&. libcpuid developers can later import this file and debug the detection code as if running on the actual hardware\&. The file is simple text format of "something=value" pairs\&. Version info is also written, but the format is not intended to be neither backward- nor forward compatible\&. .RE .PP \fBReturns\fP .RS 4 zero if successful, and some negative number on error\&. The error message can be obtained by calling \fBcpuid_error\fP\&. .RE .PP \fBSee also\fP .RS 4 \fBcpu_error_t\fP .RE .PP .SS "void cpuid_set_verbosiness_level (int level)" .PP Sets the verbosiness level\&. When the verbosiness level is above zero, some functions might print diagnostic information about what are they doing\&. The higher the level is, the more detail is printed\&. Level zero is guaranteed to omit all such output\&. The output is written using the same machinery as the warnings, .PP \fBSee also\fP .RS 4 \fBcpuid_set_warn_function()\fP .RE .PP \fBParameters\fP .RS 4 \fIlevel\fP the desired verbosiness level\&. Useful values 0\&.\&.2 inclusive .RE .PP .SS "libcpuid_warn_fn_t cpuid_set_warn_function (libcpuid_warn_fn_t warn_fun)" .PP Sets the warning print function\&. In some cases, the internal libcpuid machinery would like to emit useful debug warnings\&. By default, these warnings are written to stderr\&. However, you can set a custom function that will receive those warnings\&. .PP \fBParameters\fP .RS 4 \fIwarn_fun\fP - the warning function you want to set\&. If NULL, warnings are disabled\&. The function takes const char* argument\&. .RE .PP \fBReturns\fP .RS 4 the current warning function\&. You can use the return value to keep the previous warning function and restore it at your discretion\&. .RE .PP .SS "int msr_serialize_raw_data (struct msr_driver_t * handle, const char * filename)" .PP Writes the raw MSR data to a text file\&. .PP \fBParameters\fP .RS 4 \fIhandle\fP - a handle to the MSR reader driver, as created by cpu_msr_driver_open .br \fIfilename\fP - the path of the file, where the serialized data should be written\&. If empty, stdout will be used\&. .RE .PP \fBNote\fP .RS 4 This is intended primarily for debugging\&. On some processor, which is not currently supported or not completely recognized by cpu_identify, one can still successfully get the raw data and write it to a file\&. libcpuid developers can later import this file and debug the detection code as if running on the actual hardware\&. The file is simple text format of "something=value" pairs\&. Version info is also written, but the format is not intended to be neither backward- nor forward compatible\&. .RE .PP \fBReturns\fP .RS 4 zero if successful, and some negative number on error\&. The error message can be obtained by calling \fBcpuid_error\fP\&. .RE .PP \fBSee also\fP .RS 4 \fBcpu_error_t\fP .RE .PP .SH "Author" .PP Generated automatically by Doxygen for libcpuid from the source code\&.