DPLL(8) Linux DPLL(8)

dpll - Digital Phase Locked Loop (DPLL) subsystem management


dpll [ OPTIONS ] device { COMMAND | help }

dpll [ OPTIONS ] pin { COMMAND | help }

dpll [ OPTIONS ] monitor

OPTIONS := { -V | --Version | -j | --json | -p | --pretty | -t | --timestamp | --tshort }

The dpll utility is used to configure and monitor Digital Phase Locked Loop (DPLL) devices and pins. DPLLs are used for clock synchronization in various hardware, particularly in telecommunications and networking equipment.

A DPLL device can lock to one or more input pins and provide synchronized output. Pins can be physical external signals (like GNSS 1PPS, SyncE), or internal oscillators.

Print the version of the dpll utility and exit.
Output results in JavaScript Object Notation (JSON).
When combined with -j, generates a pretty JSON output with indentation and newlines for better human readability.
When used with the monitor object, print a Timestamp: line before each received notification, in the same format used by ip monitor.
Like -t, but emits a more compact, ISO 8601 inline prefix “[YYYY-MM-DDTHH:MM:SS.uuuuuu]” in front of each notification instead of a separate Timestamp: line.

Display information about DPLL devices. If no arguments are specified, shows all devices in the system.

Show only the device with the specified numeric identifier.
Show only devices provided by the specified kernel module.
Show only devices with the specified 64-bit clock identifier.
Show only devices of the specified type: pps or eec.
Show only devices in the specified operating mode: manual or automatic.
Show only devices with the specified lock status: unlocked, locked, locked-ho-acq, holdover.

Output includes:

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Device ID
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Module name providing the device
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Clock ID (unique identifier)
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Operating mode (manual, automatic)
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Lock status (unlocked, locked, locked-ho-acq, holdover)
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Lock status error (if present)
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Clock quality level (if supported)
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Temperature (if supported)
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Type (PPS or EEC)
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Supported modes
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Phase offset monitor status (enable/disable)
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Phase offset averaging factor
•
Frequency monitor status (enable/disable)

Configure DPLL device parameters.

Specifies which device to configure (required).
Set the operating mode of the DPLL device. In automatic mode, the DPLL autonomously selects the best available input source based on priority and quality. In manual mode, the input source must be explicitly configured and the DPLL will not automatically switch sources.
Enable or disable phase offset monitoring between the device and its pins. When enabled, the kernel continuously measures and reports phase differences.
Set the averaging factor (1-255) applied to phase offset calculations. Higher values provide smoother but slower-responding measurements.
Enable or disable frequency monitoring on the device. When enabled, the kernel continuously measures and reports actual pin frequencies, which can be read via the measured-frequency field in pin show output.

Retrieve the device ID based on identifying attributes. Useful for scripting when you need to find a device's numeric ID. At least one attribute should be specified to identify the device.

Kernel module name.
64-bit clock identifier in decimal or hex (0x prefix).
Device type: pps or eec.

Display information about DPLL pins. If no arguments are specified, shows all pins in the system.

Show only the pin with the specified numeric identifier.
Show only pins that have the specified DPLL device as a parent.
Show only pins that have the specified pin as a parent (mux pins).
Show only pins provided by the specified kernel module.
Show only pins with the specified 64-bit clock identifier.
Show only pins with the specified board label.
Show only pins with the specified panel label.
Show only pins with the specified package label.
Show only pins of the specified type: mux, ext, synce-eth-port, int-oscillator, gnss.
Show only pins that have a parent-device relationship with the specified direction: input, output. When combined with parent-device, only the specified parent-device relationship is checked.
Show only pins that have a parent-device relationship with the specified state: connected, disconnected, selectable. When combined with parent-device, only the specified parent-device relationship is checked.
Show only pins that have a parent-device relationship with the specified operational state: active, standby, no-signal, qual-failed. When combined with parent-device, only the specified parent-device relationship is checked.

Output includes:

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Pin ID
•
Module name
•
Clock ID
•
Board label (hardware label from device tree or ACPI)
•
Panel label
•
Package label
•
Pin type (mux, ext, synce-eth-port, int-oscillator, gnss)
•
Configured frequency and supported frequency ranges
•
Measured frequency in Hz (when frequency monitoring is enabled)
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Capabilities (state-can-change, priority-can-change, direction-can-change)
•
Phase adjustment range, granularity, and current value
•
Fractional frequency offset
•
Parent device relationships (direction, priority, state, phase offset)
•
Parent pin relationships
•
Reference sync information
•
Esync frequency and pulse support (if applicable)

Configure DPLL pin parameters. Multiple parameters can be specified in a single command.

Specifies which pin to configure (required).
Set pin frequency in Hz. The pin must support the specified frequency (check frequency-supported ranges in pin show output).
Set phase adjustment in picoseconds. This value fine-tunes the phase of the output signal. Negative values shift the phase backwards, positive values shift it forwards. The value must be within the phase-adjust-min and phase-adjust-max range.
Set enhanced SyncE (Synchronous Ethernet) frequency in Hz for capable pins.
Configure the relationship between this pin and a parent DPLL device.
Set the pin's direction relative to the parent device.
Set priority (0-255) for this pin on the parent device.
Set the pin's state on the parent device.
Configure the relationship to a parent pin.
Configure reference sync relationship with another pin.

Retrieve a pin ID based on identifying attributes.

Filter by kernel module name.
Filter by 64-bit clock identifier.
Filter by board label (hardware identifier).
Filter by panel label.
Filter by package label.
Filter by pin type: mux, ext, synce-eth-port, int-oscillator, gnss.

Monitor DPLL subsystem events in real-time. Displays notifications about:

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Device creation, deletion, and configuration changes
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Pin creation, deletion, and configuration changes
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Lock status changes
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Phase offset updates
•
Frequency changes

Events are prefixed with their type: [DEVICE_CREATE], [DEVICE_CHANGE], [DEVICE_DELETE], [PIN_CREATE], [PIN_CHANGE], [PIN_DELETE].

Press Ctrl+C to stop monitoring.

dpll device show

dpll -j device show id 0

dpll device set id 0 mode manual

dpll device set id 0 phase-offset-monitor enable

dpll device set id 0 frequency-monitor enable

dpll device show type eec

dpll -jp device show module-name ice

dpll pin show

dpll pin show type gnss

dpll pin show type gnss module-name ice

dpll -jp pin show id 5

dpll pin show parent-device 0 direction input state connected

dpll pin set id 0 frequency 10000000

dpll pin set id 1 parent-device 0 prio 10 direction input state connected

dpll pin set id 2 phase-adjust -1000

dpll pin set id 3 frequency 10000000 phase-adjust -1000

dpll monitor

dpll -jp monitor

dpll device id-get module-name ice

dpll pin id-get board-label GNSS-1PPS

Phase adjustment is specified in picoseconds (1e-12 seconds) and allows fine-tuning of signal phase. This is crucial for precise time synchronization applications like 5G networks and high-frequency trading.

Important considerations:

•
Check phase-adjust-min and phase-adjust-max before setting values
•
Some hardware requires values to be multiples of phase-adjust-gran
•
Negative values shift phase backwards (earlier in time)
•
Positive values shift phase forwards (later in time)
•
The kernel validates all phase adjustment requests

Pins may have various capabilities that determine which operations are allowed:

The pin's state (connected/disconnected/selectable) can be modified.
The pin's priority can be modified. This may apply to top-level priority or priority within parent-device relationships.
The pin's direction (input/output) can be modified.

Use dpll pin show to check which capabilities a pin supports before attempting configuration changes.

0
Success
1
Failure

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The DPLL subsystem requires kernel support (CONFIG_DPLL=y or m)
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Hardware support varies by device and driver
•
Some operations require specific hardware capabilities
•
Phase offset values are measured by hardware and cannot be set directly
•
Changes to device/pin configuration may affect system clock synchronization

ip(8), devlink(8), ethtool(8)

Linux kernel documentation: Documentation/driver-api/dpll.rst

Netlink specification: Documentation/netlink/specs/dpll.yaml

dpll was written by Arkadiusz Kubalewski, Vadim Fedorenko, and others.

This manual page was written by Petr Oros.

Report bugs to <netdev@vger.kernel.org>

23 October 2025 iproute2