CXL-LIST(1) cxl Manual CXL-LIST(1) (NAME) cxl-list - CXL json (SYNOPSIS) cxl list [] CXL . . json . ( ) . : "anon memdevs" ( ) "buses" "ports" buses "endpoints" ports buses ( ) "memdevs" endpoints ports ( endpoints ) buses ( endpoints ports ) "root decoders" buses "port decoders" ports buses ( ) "endpoint decoders" endpoints ports ( endpoints ) buses ( endpoints ports ) . ( "-m mem0,mem1,mem2") OR . ( "-m mem0,mem1,mem2 -p port10") AND . "-m mem0,mem1,mem2 -p port10" port10 mem0 mem1 mem2 . memdev memdev . : # cxl list -P -p switch,endpoint -m mem0 [ { "port":"port1", "host":"ACPI0016:00", "endpoints:port1":[ { "endpoint":"endpoint2", "host":"mem0" } ] } ] interleave memdev root decoder . # cxl list -Mu -d decoder0.0 { "memdev":"mem0", "pmem_size":"256.00 MiB (268.44 MB)", "serial":"0", "host":"0000:35:00.0" } -m/--memdev= -p/--port= -e/--endpoint= CXL . -m/--memdev= PCI "DDDD:bb:dd.f" (D: b: d: f: ) ( /sys/bus/pci/devices ) -p/--port= PCI "DDDD:bb:dd.f" PCI "pciDDDD:bb" -e/--endpoint= CXL "memX" . --human (unwrap) . (EXAMPLE) # cxl list --memdevs [ { "memdev":"mem0", "pmem_size":268435456, "serial":0, "host":"0000:35:00.0" } ] # cxl list -BMu [ { "anon memdevs":[ { "memdev":"mem0", "pmem_size":"256.00 MiB (268.44 MB)", "serial":"0" } ] }, { "buses":[ { "bus":"root0", "provider":"ACPI.CXL" } ] } ] (OPTIONS) -m, --memdev= () CXL ("mem0") () ("0") / () ("0000:35:00.0") . : # cxl list -M --memdev="0 mem3 5" [ { "memdev":"mem0", "pmem_size":268435456, "serial":0 }, { "memdev":"mem3", "pmem_size":268435456, "ram_size":268435456, "serial":2 }, { "memdev":"mem5", "pmem_size":268435456, "ram_size":268435456, "serial":4 } ] -s, --serial= () CXL . -M, --memdevs CXL . -i, --idle ( / ) . -H, --health memdev. : # cxl list -m mem0 -H [ { "memdev":"mem0", "pmem_size":268435456, "ram_size":268435456, "health":{ "maintenance_needed":true, "performance_degraded":true, "hw_replacement_needed":true, "media_normal":false, "media_not_ready":false, "media_persistence_lost":false, "media_data_lost":true, "media_powerloss_persistence_loss":false, "media_shutdown_persistence_loss":false, "media_persistence_loss_imminent":false, "media_powerloss_data_loss":false, "media_shutdown_data_loss":false, "media_data_loss_imminent":false, "ext_life_used":"normal", "ext_temperature":"critical", "ext_corrected_volatile":"warning", "ext_corrected_persistent":"normal", "life_used_percent":15, "temperature":25, "dirty_shutdowns":10, "volatile_errors":20, "pmem_errors":30 } } ] -I, --partition memdev. : # cxl list -m mem0 -I [ { "memdev":"mem0", "ram_size":273535729664, "partition_info":{ "total_size":273535729664, "volatile_only_size":0, "persistent_only_size":0, "partition_alignment_size":268435456 "active_volatile_size":273535729664, "active_persistent_size":0, "next_volatile_size":0, "next_persistent_size":0, } } ] -A, --alert-config memdev. : # cxl list -m mem0 -A [ { "memdev":"mem0", "pmem_size":0, "ram_size":273535729664, "alert_config":{ "life_used_prog_warn_threshold_valid":false, "dev_over_temperature_prog_warn_threshold_valid":false, "dev_under_temperature_prog_warn_threshold_valid":false, "corrected_volatile_mem_err_prog_warn_threshold_valid":true, "corrected_pmem_err_prog_warn_threshold_valid":false, "life_used_prog_warn_threshold_writable":false, "dev_over_temperature_prog_warn_threshold_writable":false, "dev_under_temperature_prog_warn_threshold_writable":false, "corrected_volatile_mem_err_prog_warn_threshold_writable":true, "corrected_pmem_err_prog_warn_threshold_writable":false, "life_used_crit_alert_threshold":0, "life_used_prog_warn_threshold":0, "dev_over_temperature_crit_alert_threshold":0, "dev_under_temperature_crit_alert_threshold":0, "dev_over_temperature_prog_warn_threshold":0, "dev_under_temperature_prog_warn_threshold":0, "corrected_volatile_mem_err_prog_warn_threshold":0, "corrected_pmem_err_prog_warn_threshold":0 }, } ] -B, --buses () bus / CXL . ACPI (singleton) ACPI0017 CXL . # cxl list -B [ { "bus":"root3", "provider":"cxl_test" }, { "bus":"root0", "provider":"ACPI.CXL" } ] -b, --bus= () CXL () / CXL . "ACPI.CXL" "cxl_test" . -P, --ports ( CXL / PCIe + ) . -p, --port= () CXL ("port2") () ("2") () ("pci0000:34") / () . "root" "switch" . : # cxl list -B # cxl list -P -p root -S ... '-S/--single' '-S/--single' . '-S/--single' : # cxl list -E # cxl list -P -p endpoint 'switch' # cxl list -P # cxl list -P -p switch ... . -S, --single . . -E, --endpoints ( CXL) . # cxl list -E [ { "endpoint":"endpoint2", "host":"mem0" } ] -e, --endpoint () CXL () () . -D, --decoders ( CXL ) . -d, --decoder () CXL () () . "decoder." . "root" "switch" "endpoint" . -T, --targets / . # cxl list -BTu -b ACPI.CXL { "bus":"root0", "provider":"ACPI.CXL", "nr_dports":1, "dports":[ { "dport":"ACPI0016:00", "alias":"pci0000:34", "id":"0" } ] } -R, --regions (region) . # cxl list -R { "region":"region0", "resource":277025390592, "size":549755813888, "extended_linear_cache_size":274877906944, "type":"ram", "interleave_ways":2, "interleave_granularity":256, "decode_state":"commit", "qos_class_mismatch":true } -X, --dax DAX . # cxl list -RXu { "region":"region4", "resource":"0xf010000000", "size":"512.00 MiB (536.87 MB)", "interleave_ways":2, "interleave_granularity":4096, "decode_state":"commit", "daxregion":{ "id":4, "size":"512.00 MiB (536.87 MB)", "align":2097152, "devices":[ { "chardev":"dax4.0", "size":"512.00 MiB (536.87 MB)", "target_node":0, "align":2097152, "mode":"system-ram", "online_memblocks":0, "total_memblocks":4 } ] } } -r, --region () CXL () . -L, --media-errors (media-error). poison () media_error . memdev poison . "offset:" memdev DPA . "source:" : External Internal Injected Vendor Specific Unknown 8-140 CXL 3.1 . media-errors -Dlibtracefs=enabled . # cxl list -m mem9 --media-errors -u { "memdev":"mem9", "pmem_size":"1024.00 MiB (1073.74 MB)", "pmem_qos_class":42, "ram_size":"1024.00 MiB (1073.74 MB)", "ram_qos_class":42, "serial":"0x5", "numa_node":1, "host":"cxl_mem.5", "media_errors":[ { "offset":"0x40000000", "length":64, "source":"Injected" } ] } # cxl list -r region5 --media-errors -u { "region":"region5", "resource":"0xf110000000", "size":"2.00 GiB (2.15 GB)", "type":"pmem", "interleave_ways":2, "interleave_granularity":4096, "decode_state":"commit", "media_errors":[ { "offset":"0x1000", "length":64, "source":"Injected" }, { "offset":"0x2000", "length":64, "source":"Injected" } ] } -v, --verbose . . cxl list --verbose --verbose cxl list -vv . o -v --memdevs --regions --buses --ports --decoders --targets. o -vv -v --idle. o -vvv -vv --health --partition --media-errors. --debug cxl . -u, --human . . (COPYRIGHT) (C) 2016 - 2022 (Intel Corporation). GPLv2: GPL . : . . (SEE ALSO) ndctl-list(1) cxl 2026-06-30 CXL-LIST(1)